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net/hns3: add more hardware error types

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The new firmware adds the hardware error types reported by MSI-x mode.

These errors are defined as RAS errors in hardware and belong to a
different type from the MSI-x errors processed by the driver.

When hardware detects an error which must be handled by the driver for
device to run properly it reports the error information through the
MSI-x interrupt. After receiving the interrupt reported by the hardware,
the driver queries the error information and identifies the error level,
then rectifies the error. All errors will be logged.
In addition, the hardware may be reset at the function or global level
based on the error level. After the reset is complete, the hardware will
recover to the normal status.

Signed-off-by: Hongbo Zheng <zhenghongbo3@huawei.com>
Signed-off-by: Wei Hu (Xavier) <xavier.huwei@huawei.com>
This commit is contained in:
Wei Hu (Xavier) 2020-08-25 19:52:59 +08:00 committed by Ferruh Yigit
parent 395b5e08ef
commit f53a793bb7
8 changed files with 1246 additions and 254 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

46
drivers/net/hns3/hns3_cmd.h
View File

@ -100,7 +100,6 @@ enum hns3_opcode_type {
HNS3_OPC_QUERY_LINK_STATUS = 0x0307,
HNS3_OPC_CONFIG_MAX_FRM_SIZE = 0x0308,
HNS3_OPC_CONFIG_SPEED_DUP = 0x0309,
HNS3_MAC_COMMON_INT_EN = 0x030E,
/* PFC/Pause commands */
HNS3_OPC_CFG_MAC_PAUSE_EN = 0x0701,
@ -153,10 +152,6 @@ enum hns3_opcode_type {
HNS3_OPC_RX_COM_THRD_ALLOC = 0x0904,
HNS3_OPC_RX_COM_WL_ALLOC = 0x0905,
/* SSU module INT commands */
HNS3_SSU_ECC_INT_CMD = 0x0989,
HNS3_SSU_COMMON_INT_CMD = 0x098C,
/* TQP management command */
HNS3_OPC_SET_TQP_MAP = 0x0A01,
@ -166,11 +161,6 @@ enum hns3_opcode_type {
HNS3_OPC_CFG_COM_TQP_QUEUE = 0x0B20,
HNS3_OPC_RESET_TQP_QUEUE = 0x0B22,
/* PPU module intr commands */
HNS3_PPU_MPF_ECC_INT_CMD = 0x0B40,
HNS3_PPU_MPF_OTHER_INT_CMD = 0x0B41,
HNS3_PPU_PF_OTHER_INT_CMD = 0x0B42,
/* TSO command */
HNS3_OPC_TSO_GENERIC_CONFIG = 0x0C01,
HNS3_OPC_GRO_GENERIC_CONFIG = 0x0C10,
@ -216,17 +206,30 @@ enum hns3_opcode_type {
HNS3_OPC_SFP_GET_SPEED = 0x7104,
/* Interrupts commands */
HNS3_OPC_ADD_RING_TO_VECTOR = 0x1503,
HNS3_OPC_DEL_RING_TO_VECTOR = 0x1504,
HNS3_OPC_ADD_RING_TO_VECTOR = 0x1503,
HNS3_OPC_DEL_RING_TO_VECTOR = 0x1504,
/* Error INT commands */
HNS3_QUERY_MSIX_INT_STS_BD_NUM = 0x1513,
HNS3_QUERY_CLEAR_ALL_MPF_MSIX_INT = 0x1514,
HNS3_QUERY_CLEAR_ALL_PF_MSIX_INT = 0x1515,
/* PPP module intr commands */
HNS3_PPP_CMD0_INT_CMD = 0x2100,
HNS3_PPP_CMD1_INT_CMD = 0x2101,
HNS3_OPC_MAC_COMMON_INT_EN = 0x030E,
HNS3_OPC_TM_SCH_ECC_INT_EN = 0x0829,
HNS3_OPC_SSU_ECC_INT_CMD = 0x0989,
HNS3_OPC_SSU_COMMON_INT_CMD = 0x098C,
HNS3_OPC_PPU_MPF_ECC_INT_CMD = 0x0B40,
HNS3_OPC_PPU_MPF_OTHER_INT_CMD = 0x0B41,
HNS3_OPC_PPU_PF_OTHER_INT_CMD = 0x0B42,
HNS3_OPC_COMMON_ECC_INT_CFG = 0x1505,
HNS3_OPC_QUERY_RAS_INT_STS_BD_NUM = 0x1510,
HNS3_OPC_QUERY_CLEAR_MPF_RAS_INT = 0x1511,
HNS3_OPC_QUERY_CLEAR_PF_RAS_INT = 0x1512,
HNS3_OPC_QUERY_MSIX_INT_STS_BD_NUM = 0x1513,
HNS3_OPC_QUERY_CLEAR_ALL_MPF_MSIX_INT = 0x1514,
HNS3_OPC_QUERY_CLEAR_ALL_PF_MSIX_INT = 0x1515,
HNS3_OPC_IGU_EGU_TNL_INT_EN = 0x1803,
HNS3_OPC_IGU_COMMON_INT_EN = 0x1806,
HNS3_OPC_TM_QCN_MEM_INT_CFG = 0x1A14,
HNS3_OPC_PPP_CMD0_INT_CMD = 0x2100,
HNS3_OPC_PPP_CMD1_INT_CMD = 0x2101,
HNS3_OPC_NCSI_INT_EN = 0x2401,
};
#define HNS3_CMD_FLAG_IN BIT(0)
@ -236,6 +239,11 @@ enum hns3_opcode_type {
#define HNS3_CMD_FLAG_NO_INTR BIT(4)
#define HNS3_CMD_FLAG_ERR_INTR BIT(5)
#define HNS3_MPF_RAS_INT_MIN_BD_NUM 10
#define HNS3_PF_RAS_INT_MIN_BD_NUM 4
#define HNS3_MPF_MSIX_INT_MIN_BD_NUM 10
#define HNS3_PF_MSIX_INT_MIN_BD_NUM 4
#define HNS3_BUF_SIZE_UNIT 256
#define HNS3_BUF_MUL_BY 2
#define HNS3_BUF_DIV_BY 2

67
drivers/net/hns3/hns3_ethdev.c
View File

@ -56,6 +56,9 @@
#define HNS3_FUN_RST_ING_B 0
#define HNS3_VECTOR0_IMP_RESET_INT_B 1
#define HNS3_VECTOR0_IMP_CMDQ_ERR_B 4U
#define HNS3_VECTOR0_IMP_RD_POISON_B 5U
#define HNS3_VECTOR0_ALL_MSIX_ERR_B 6U
#define HNS3_RESET_WAIT_MS 100
#define HNS3_RESET_WAIT_CNT 200
@ -97,12 +100,14 @@ hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
struct hns3_hw *hw = &hns->hw;
uint32_t vector0_int_stats;
uint32_t cmdq_src_val;
uint32_t hw_err_src_reg;
uint32_t val;
enum hns3_evt_cause ret;
/* fetch the events from their corresponding regs */
vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
hw_err_src_reg = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
/*
* Assumption: If by any chance reset and mailbox events are reported
@ -145,8 +150,9 @@ hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
}
/* check for vector0 msix event source */
if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK) {
val = vector0_int_stats;
if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK ||
hw_err_src_reg & HNS3_RAS_REG_NFE_MASK) {
val = vector0_int_stats | hw_err_src_reg;
ret = HNS3_VECTOR0_EVENT_ERR;
goto out;
}
@ -159,9 +165,9 @@ hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
goto out;
}
if (clearval && (vector0_int_stats || cmdq_src_val))
hns3_warn(hw, "surprise irq ector0_int_stats:0x%x cmdq_src_val:0x%x",
vector0_int_stats, cmdq_src_val);
if (clearval && (vector0_int_stats || cmdq_src_val || hw_err_src_reg))
hns3_warn(hw, "vector0_int_stats:0x%x cmdq_src_val:0x%x hw_err_src_reg:0x%x",
vector0_int_stats, cmdq_src_val, hw_err_src_reg);
val = vector0_int_stats;
ret = HNS3_VECTOR0_EVENT_OTHER;
out:
@ -215,11 +221,14 @@ hns3_interrupt_handler(void *param)
/* vector 0 interrupt is shared with reset and mailbox source events. */
if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
hns3_warn(hw, "Received err interrupt");
hns3_handle_msix_error(hns, &hw->reset.request);
hns3_handle_ras_error(hns, &hw->reset.request);
hns3_schedule_reset(hns);
} else if (event_cause == HNS3_VECTOR0_EVENT_RST)
} else if (event_cause == HNS3_VECTOR0_EVENT_RST) {
hns3_warn(hw, "Received reset interrupt");
hns3_schedule_reset(hns);
else if (event_cause == HNS3_VECTOR0_EVENT_MBX)
} else if (event_cause == HNS3_VECTOR0_EVENT_MBX)
hns3_dev_handle_mbx_msg(hw);
else
hns3_err(hw, "Received unknown event");
@ -4425,6 +4434,24 @@ hns3_clear_hw(struct hns3_hw *hw)
return 0;
}
static void
hns3_config_all_msix_error(struct hns3_hw *hw, bool enable)
{
uint32_t val;
/*
* The new firmware support report more hardware error types by
* msix mode. These errors are defined as RAS errors in hardware
* and belong to a different type from the MSI-x errors processed
* by the network driver.
*
* Network driver should open the new error report on initialition
*/
val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
hns3_set_bit(val, HNS3_VECTOR0_ALL_MSIX_ERR_B, enable ? 1 : 0);
hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, val);
}
static int
hns3_init_pf(struct rte_eth_dev *eth_dev)
{
@ -4467,6 +4494,8 @@ hns3_init_pf(struct rte_eth_dev *eth_dev)
goto err_cmd_init;
}
hns3_config_all_msix_error(hw, true);
ret = rte_intr_callback_register(&pci_dev->intr_handle,
hns3_interrupt_handler,
eth_dev);
@ -4550,6 +4579,7 @@ hns3_uninit_pf(struct rte_eth_dev *eth_dev)
rte_intr_disable(&pci_dev->intr_handle);
hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
eth_dev);
hns3_config_all_msix_error(hw, false);
hns3_cmd_uninit(hw);
hns3_cmd_destroy_queue(hw);
hw->io_base = NULL;
@ -5234,6 +5264,28 @@ hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels)
return reset_level;
}
static void
hns3_record_imp_error(struct hns3_adapter *hns)
{
struct hns3_hw *hw = &hns->hw;
uint32_t reg_val;
reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B)) {
hns3_warn(hw, "Detected IMP RD poison!");
hns3_error_int_stats_add(hns, "IMP_RD_POISON_INT_STS");
hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B, 0);
hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
}
if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B)) {
hns3_warn(hw, "Detected IMP CMDQ error!");
hns3_error_int_stats_add(hns, "CMDQ_MEM_ECC_INT_STS");
hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B, 0);
hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
}
}
static int
hns3_prepare_reset(struct hns3_adapter *hns)
{
@ -5257,6 +5309,7 @@ hns3_prepare_reset(struct hns3_adapter *hns)
hw->reset.stats.request_cnt++;
break;
case HNS3_IMP_RESET:
hns3_record_imp_error(hns);
reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val |
BIT(HNS3_VECTOR0_IMP_RESET_INT_B));

34
drivers/net/hns3/hns3_ethdev.h
View File

@ -491,11 +491,35 @@ struct hns3_hw {
#define HNS3_FLAG_VNET_BASE_SCH_MODE 2
struct hns3_err_msix_intr_stats {
uint64_t mac_afifo_tnl_intr_cnt;
uint64_t ppu_mpf_abnormal_intr_st2_cnt;
uint64_t ssu_port_based_pf_intr_cnt;
uint64_t ppp_pf_abnormal_intr_cnt;
uint64_t ppu_pf_abnormal_intr_cnt;
uint64_t mac_afifo_tnl_int_cnt;
uint64_t ppu_mpf_abn_int_st2_msix_cnt;
uint64_t ssu_port_based_pf_int_cnt;
uint64_t ppp_pf_abnormal_int_cnt;
uint64_t ppu_pf_abnormal_int_msix_cnt;
uint64_t imp_tcm_ecc_int_cnt;
uint64_t cmdq_mem_ecc_int_cnt;
uint64_t imp_rd_poison_int_cnt;
uint64_t tqp_int_ecc_int_cnt;
uint64_t msix_ecc_int_cnt;
uint64_t ssu_ecc_multi_bit_int_0_cnt;
uint64_t ssu_ecc_multi_bit_int_1_cnt;
uint64_t ssu_common_ecc_int_cnt;
uint64_t igu_int_cnt;
uint64_t ppp_mpf_abnormal_int_st1_cnt;
uint64_t ppp_mpf_abnormal_int_st3_cnt;
uint64_t ppu_mpf_abnormal_int_st1_cnt;
uint64_t ppu_mpf_abn_int_st2_ras_cnt;
uint64_t ppu_mpf_abnormal_int_st3_cnt;
uint64_t tm_sch_int_cnt;
uint64_t qcn_fifo_int_cnt;
uint64_t qcn_ecc_int_cnt;
uint64_t ncsi_ecc_int_cnt;
uint64_t ssu_port_based_err_int_cnt;
uint64_t ssu_fifo_overflow_int_cnt;
uint64_t ssu_ets_tcg_int_cnt;
uint64_t igu_egu_tnl_int_cnt;
uint64_t ppu_pf_abnormal_int_ras_cnt;
};
/* vlan entry information. */

1230
drivers/net/hns3/hns3_intr.c
View File

File diff suppressed because it is too large Load Diff

40
drivers/net/hns3/hns3_intr.h
View File

@ -19,6 +19,22 @@
#define HNS3_MAC_COMMON_ERR_INT_EN 0x107FF
#define HNS3_MAC_COMMON_ERR_INT_EN_MASK 0x107FF
#define HNS3_IMP_TCM_ECC_ERR_INT_EN 0xFFFF0000
#define HNS3_IMP_TCM_ECC_ERR_INT_EN_MASK 0xFFFF0000
#define HNS3_IMP_ITCM4_ECC_ERR_INT_EN 0x300
#define HNS3_IMP_ITCM4_ECC_ERR_INT_EN_MASK 0x300
#define HNS3_IMP_RD_POISON_ERR_INT_EN 0x0100
#define HNS3_IMP_RD_POISON_ERR_INT_EN_MASK 0x0100
#define HNS3_CMDQ_NIC_ECC_ERR_INT_EN 0xFFFF
#define HNS3_CMDQ_NIC_ECC_ERR_INT_EN_MASK 0xFFFF
#define HNS3_TQP_ECC_ERR_INT_EN 0x0FFF
#define HNS3_TQP_ECC_ERR_INT_EN_MASK 0x0FFF
#define HNS3_MSIX_SRAM_ECC_ERR_INT_EN 0x0F000000
#define HNS3_MSIX_SRAM_ECC_ERR_INT_EN_MASK 0x0F000000
#define HNS3_PPU_MPF_ABNORMAL_INT0_EN GENMASK(31, 0)
#define HNS3_PPU_MPF_ABNORMAL_INT0_EN_MASK GENMASK(31, 0)
#define HNS3_PPU_MPF_ABNORMAL_INT1_EN GENMASK(31, 0)
@ -31,8 +47,6 @@
#define HNS3_PPU_MPF_ABNORMAL_INT3_EN_MASK GENMASK(23, 16)
#define HNS3_PPU_PF_ABNORMAL_INT_EN GENMASK(5, 0)
#define HNS3_PPU_PF_ABNORMAL_INT_EN_MASK GENMASK(5, 0)
#define HNS3_PPU_PF_INT_MSIX_MASK 0x27
#define HNS3_PPU_MPF_INT_ST2_MSIX_MASK GENMASK(29, 28)
#define HNS3_SSU_1BIT_ECC_ERR_INT_EN GENMASK(31, 0)
#define HNS3_SSU_1BIT_ECC_ERR_INT_EN_MASK GENMASK(31, 0)
@ -46,8 +60,17 @@
#define HNS3_SSU_PORT_BASED_ERR_INT_EN_MASK 0x0BFF0000
#define HNS3_SSU_FIFO_OVERFLOW_ERR_INT_EN GENMASK(23, 0)
#define HNS3_SSU_FIFO_OVERFLOW_ERR_INT_EN_MASK GENMASK(23, 0)
#define HNS3_SSU_COMMON_ERR_INT_MASK GENMASK(9, 0)
#define HNS3_SSU_PORT_INT_MSIX_MASK 0x7BFF
#define HNS3_IGU_ERR_INT_ENABLE 0x0000066F
#define HNS3_IGU_ERR_INT_DISABLE 0x00000660
#define HNS3_IGU_ERR_INT_EN_MASK 0x000F
#define HNS3_IGU_TNL_ERR_INT_EN 0x0002AABF
#define HNS3_IGU_TNL_ERR_INT_EN_MASK 0x003F
#define HNS3_NCSI_ERR_INT_EN 0x3
#define HNS3_TM_SCH_ECC_ERR_INT_EN 0x3
#define HNS3_TM_QCN_MEM_ERR_INT_EN 0xFFFFFF
#define HNS3_RESET_PROCESS_MS 200
@ -62,8 +85,17 @@ struct hns3_hw_error {
enum hns3_reset_level reset_level;
};
struct hns3_hw_error_desc {
uint8_t desc_offset;
uint8_t data_offset;
const char *msg;
const struct hns3_hw_error *hw_err;
};
int hns3_enable_hw_error_intr(struct hns3_adapter *hns, bool state);
void hns3_handle_msix_error(struct hns3_adapter *hns, uint64_t *levels);
void hns3_handle_ras_error(struct hns3_adapter *hns, uint64_t *levels);
void hns3_intr_unregister(const struct rte_intr_handle *hdl,
rte_intr_callback_fn cb_fn, void *cb_arg);
void hns3_notify_reset_ready(struct hns3_hw *hw, bool enable);

3
drivers/net/hns3/hns3_regs.h
View File

@ -27,6 +27,9 @@
#define HNS3_VECTOR0_OTHER_INT_STS_REG 0x20800
#define HNS3_RAS_PF_OTHER_INT_STS_REG 0x20B00
#define HNS3_RAS_REG_NFE_MASK 0xFF00
#define HNS3_MISC_VECTOR_REG_BASE 0x20400
#define HNS3_VECTOR0_OTER_EN_REG 0x20600
#define HNS3_MISC_RESET_STS_REG 0x20700

78
drivers/net/hns3/hns3_stats.c
View File

@ -189,15 +189,61 @@ static const struct hns3_xstats_name_offset hns3_mac_strings[] = {
static const struct hns3_xstats_name_offset hns3_error_int_stats_strings[] = {
{"MAC_AFIFO_TNL_INT_R",
HNS3_ERR_INT_STATS_FIELD_OFFSET(mac_afifo_tnl_intr_cnt)},
{"PPU_MPF_ABNORMAL_INT_ST2",
HNS3_ERR_INT_STATS_FIELD_OFFSET(ppu_mpf_abnormal_intr_st2_cnt)},
{"SSU_PORT_BASED_ERR_INT",
HNS3_ERR_INT_STATS_FIELD_OFFSET(ssu_port_based_pf_intr_cnt)},
HNS3_ERR_INT_STATS_FIELD_OFFSET(mac_afifo_tnl_int_cnt)},
{"PPU_MPF_ABNORMAL_INT_ST2_MSIX",
HNS3_ERR_INT_STATS_FIELD_OFFSET(ppu_mpf_abn_int_st2_msix_cnt)},
{"SSU_PORT_BASED_ERR_INT_MSIX",
HNS3_ERR_INT_STATS_FIELD_OFFSET(ssu_port_based_pf_int_cnt)},
{"PPP_PF_ABNORMAL_INT_ST0",
HNS3_ERR_INT_STATS_FIELD_OFFSET(ppp_pf_abnormal_intr_cnt)},
{"PPU_PF_ABNORMAL_INT_ST",
HNS3_ERR_INT_STATS_FIELD_OFFSET(ppu_pf_abnormal_intr_cnt)}
HNS3_ERR_INT_STATS_FIELD_OFFSET(ppp_pf_abnormal_int_cnt)},
{"PPU_PF_ABNORMAL_INT_ST_MSIX",
HNS3_ERR_INT_STATS_FIELD_OFFSET(ppu_pf_abnormal_int_msix_cnt)},
{"IMP_TCM_ECC_INT_STS",
HNS3_ERR_INT_STATS_FIELD_OFFSET(imp_tcm_ecc_int_cnt)},
{"CMDQ_MEM_ECC_INT_STS",
HNS3_ERR_INT_STATS_FIELD_OFFSET(cmdq_mem_ecc_int_cnt)},
{"IMP_RD_POISON_INT_STS",
HNS3_ERR_INT_STATS_FIELD_OFFSET(imp_rd_poison_int_cnt)},
{"TQP_INT_ECC_INT_STS",
HNS3_ERR_INT_STATS_FIELD_OFFSET(tqp_int_ecc_int_cnt)},
{"MSIX_ECC_INT_STS",
HNS3_ERR_INT_STATS_FIELD_OFFSET(msix_ecc_int_cnt)},
{"SSU_ECC_MULTI_BIT_INT_0",
HNS3_ERR_INT_STATS_FIELD_OFFSET(ssu_ecc_multi_bit_int_0_cnt)},
{"SSU_ECC_MULTI_BIT_INT_1",
HNS3_ERR_INT_STATS_FIELD_OFFSET(ssu_ecc_multi_bit_int_1_cnt)},
{"SSU_COMMON_ERR_INT",
HNS3_ERR_INT_STATS_FIELD_OFFSET(ssu_common_ecc_int_cnt)},
{"IGU_INT_STS",
HNS3_ERR_INT_STATS_FIELD_OFFSET(igu_int_cnt)},
{"PPP_MPF_ABNORMAL_INT_ST1",
HNS3_ERR_INT_STATS_FIELD_OFFSET(ppp_mpf_abnormal_int_st1_cnt)},
{"PPP_MPF_ABNORMAL_INT_ST3",
HNS3_ERR_INT_STATS_FIELD_OFFSET(ppp_mpf_abnormal_int_st3_cnt)},
{"PPU_MPF_ABNORMAL_INT_ST1",
HNS3_ERR_INT_STATS_FIELD_OFFSET(ppu_mpf_abnormal_int_st1_cnt)},
{"PPU_MPF_ABNORMAL_INT_ST2_RAS",
HNS3_ERR_INT_STATS_FIELD_OFFSET(ppu_mpf_abn_int_st2_ras_cnt)},
{"PPU_MPF_ABNORMAL_INT_ST3",
HNS3_ERR_INT_STATS_FIELD_OFFSET(ppu_mpf_abnormal_int_st3_cnt)},
{"TM_SCH_RINT",
HNS3_ERR_INT_STATS_FIELD_OFFSET(tm_sch_int_cnt)},
{"QCN_FIFO_RINT",
HNS3_ERR_INT_STATS_FIELD_OFFSET(qcn_fifo_int_cnt)},
{"QCN_ECC_RINT",
HNS3_ERR_INT_STATS_FIELD_OFFSET(qcn_ecc_int_cnt)},
{"NCSI_ECC_INT_RPT",
HNS3_ERR_INT_STATS_FIELD_OFFSET(ncsi_ecc_int_cnt)},
{"SSU_PORT_BASED_ERR_INT_RAS",
HNS3_ERR_INT_STATS_FIELD_OFFSET(ssu_port_based_err_int_cnt)},
{"SSU_FIFO_OVERFLOW_INT",
HNS3_ERR_INT_STATS_FIELD_OFFSET(ssu_fifo_overflow_int_cnt)},
{"SSU_ETS_TCG_INT",
HNS3_ERR_INT_STATS_FIELD_OFFSET(ssu_ets_tcg_int_cnt)},
{"IGU_EGU_TNL_INT_STS",
HNS3_ERR_INT_STATS_FIELD_OFFSET(igu_egu_tnl_int_cnt)},
{"PPU_PF_ABNORMAL_INT_ST_RAS",
HNS3_ERR_INT_STATS_FIELD_OFFSET(ppu_pf_abnormal_int_ras_cnt)},
};
/* The statistic of reset */
@ -645,6 +691,22 @@ hns3_get_queue_stats(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
}
void
hns3_error_int_stats_add(struct hns3_adapter *hns, const char *err)
{
struct hns3_pf *pf = &hns->pf;
uint16_t i;
char *addr;
for (i = 0; i < HNS3_NUM_ERROR_INT_XSTATS; i++) {
if (strcmp(hns3_error_int_stats_strings[i].name, err) == 0) {
addr = (char *)&pf->abn_int_stats +
hns3_error_int_stats_strings[i].offset;
*(uint64_t *)addr += 1;
}
}
}
/*
* Retrieve extended(tqp | Mac) statistics of an Ethernet device.
* @param dev

2
drivers/net/hns3/hns3_stats.h
View File

@ -148,4 +148,6 @@ int hns3_dev_xstats_get_names_by_id(struct rte_eth_dev *dev,
const uint64_t *ids,
uint32_t size);
int hns3_stats_reset(struct rte_eth_dev *dev);
void hns3_error_int_stats_add(struct hns3_adapter *hns, const char *err);
#endif /* _HNS3_STATS_H_ */