bus/dpaa: add QMAN interface driver
The Queue Manager (QMan) is a hardware queue management block that allows software and accelerators on the datapath to enqueue and dequeue frames in order to communicate. This part of QBMAN DPAA Block. Signed-off-by: Geoff Thorpe <geoff.thorpe@nxp.com> Signed-off-by: Roy Pledge <roy.pledge@nxp.com> Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com> Signed-off-by: Shreyansh Jain <shreyansh.jain@nxp.com>
This commit is contained in:
Shreyansh Jain
Ferruh Yigit
parent
65ebc1be3c
commit
f6fadc3e63
@ -63,6 +63,7 @@ SRCS-$(CONFIG_RTE_LIBRTE_DPAA_BUS) += \
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base/fman/of.c \
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base/fman/netcfg_layer.c \
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base/qbman/process.c \
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base/qbman/qman_driver.c \
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base/qbman/dpaa_sys.c
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# Link Pthread
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271
drivers/bus/dpaa/base/qbman/qman_driver.c
Normal file
271
drivers/bus/dpaa/base/qbman/qman_driver.c
Normal file
@ -0,0 +1,271 @@
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/*-
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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*
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* BSD LICENSE
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*
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* Copyright 2008-2016 Freescale Semiconductor Inc.
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* Copyright 2017 NXP.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of the above-listed copyright holders nor the
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* names of any contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* GPL LICENSE SUMMARY
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*
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* ALTERNATIVELY, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") as published by the Free Software
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* Foundation, either version 2 of that License or (at your option) any
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* later version.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <fsl_usd.h>
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#include <process.h>
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#include "qman_priv.h"
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#include <sys/ioctl.h>
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#include <rte_branch_prediction.h>
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/* Global variable containing revision id (even on non-control plane systems
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* where CCSR isn't available).
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*/
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u16 qman_ip_rev;
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u16 qm_channel_pool1 = QMAN_CHANNEL_POOL1;
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u16 qm_channel_caam = QMAN_CHANNEL_CAAM;
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u16 qm_channel_pme = QMAN_CHANNEL_PME;
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/* Ccsr map address to access ccsrbased register */
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void *qman_ccsr_map;
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/* The qman clock frequency */
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u32 qman_clk;
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static __thread int fd = -1;
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static __thread struct qm_portal_config pcfg;
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static __thread struct dpaa_ioctl_portal_map map = {
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.type = dpaa_portal_qman
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};
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static int fsl_qman_portal_init(uint32_t index, int is_shared)
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{
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cpu_set_t cpuset;
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int loop, ret;
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struct dpaa_ioctl_irq_map irq_map;
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/* Verify the thread's cpu-affinity */
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ret = pthread_getaffinity_np(pthread_self(), sizeof(cpu_set_t),
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&cpuset);
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if (ret) {
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error(0, ret, "pthread_getaffinity_np()");
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return ret;
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}
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pcfg.cpu = -1;
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for (loop = 0; loop < CPU_SETSIZE; loop++)
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if (CPU_ISSET(loop, &cpuset)) {
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if (pcfg.cpu != -1) {
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pr_err("Thread is not affine to 1 cpu\n");
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return -EINVAL;
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}
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pcfg.cpu = loop;
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}
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if (pcfg.cpu == -1) {
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pr_err("Bug in getaffinity handling!\n");
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return -EINVAL;
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}
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/* Allocate and map a qman portal */
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map.index = index;
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ret = process_portal_map(&map);
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if (ret) {
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error(0, ret, "process_portal_map()");
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return ret;
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}
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pcfg.channel = map.channel;
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pcfg.pools = map.pools;
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pcfg.index = map.index;
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/* Make the portal's cache-[enabled|inhibited] regions */
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pcfg.addr_virt[DPAA_PORTAL_CE] = map.addr.cena;
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pcfg.addr_virt[DPAA_PORTAL_CI] = map.addr.cinh;
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fd = open(QMAN_PORTAL_IRQ_PATH, O_RDONLY);
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if (fd == -1) {
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pr_err("QMan irq init failed\n");
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process_portal_unmap(&map.addr);
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return -EBUSY;
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}
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pcfg.is_shared = is_shared;
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pcfg.node = NULL;
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pcfg.irq = fd;
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irq_map.type = dpaa_portal_qman;
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irq_map.portal_cinh = map.addr.cinh;
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process_portal_irq_map(fd, &irq_map);
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return 0;
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}
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static int fsl_qman_portal_finish(void)
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{
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int ret;
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process_portal_irq_unmap(fd);
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ret = process_portal_unmap(&map.addr);
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if (ret)
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error(0, ret, "process_portal_unmap()");
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return ret;
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}
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int qman_thread_init(void)
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{
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/* Convert from contiguous/virtual cpu numbering to real cpu when
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* calling into the code that is dependent on the device naming.
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*/
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return fsl_qman_portal_init(QBMAN_ANY_PORTAL_IDX, 0);
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}
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int qman_thread_finish(void)
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{
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return fsl_qman_portal_finish();
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}
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void qman_thread_irq(void)
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{
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qbman_invoke_irq(pcfg.irq);
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/* Now we need to uninhibit interrupts. This is the only code outside
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* the regular portal driver that manipulates any portal register, so
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* rather than breaking that encapsulation I am simply hard-coding the
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* offset to the inhibit register here.
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*/
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out_be32(pcfg.addr_virt[DPAA_PORTAL_CI] + 0xe0c, 0);
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}
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int qman_global_init(void)
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{
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const struct device_node *dt_node;
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int ret = 0;
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size_t lenp;
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const u32 *chanid;
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static int ccsr_map_fd;
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const uint32_t *qman_addr;
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uint64_t phys_addr;
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uint64_t regs_size;
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const u32 *clk;
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static int done;
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if (done)
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return -EBUSY;
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/* Use the device-tree to determine IP revision until something better
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* is devised.
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*/
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dt_node = of_find_compatible_node(NULL, NULL, "fsl,qman-portal");
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if (!dt_node) {
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pr_err("No qman portals available for any CPU\n");
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return -ENODEV;
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}
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if (of_device_is_compatible(dt_node, "fsl,qman-portal-1.0") ||
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of_device_is_compatible(dt_node, "fsl,qman-portal-1.0.0"))
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pr_err("QMan rev1.0 on P4080 rev1 is not supported!\n");
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else if (of_device_is_compatible(dt_node, "fsl,qman-portal-1.1") ||
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of_device_is_compatible(dt_node, "fsl,qman-portal-1.1.0"))
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qman_ip_rev = QMAN_REV11;
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else if (of_device_is_compatible(dt_node, "fsl,qman-portal-1.2") ||
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of_device_is_compatible(dt_node, "fsl,qman-portal-1.2.0"))
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qman_ip_rev = QMAN_REV12;
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else if (of_device_is_compatible(dt_node, "fsl,qman-portal-2.0") ||
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of_device_is_compatible(dt_node, "fsl,qman-portal-2.0.0"))
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qman_ip_rev = QMAN_REV20;
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else if (of_device_is_compatible(dt_node, "fsl,qman-portal-3.0.0") ||
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of_device_is_compatible(dt_node, "fsl,qman-portal-3.0.1"))
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qman_ip_rev = QMAN_REV30;
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else if (of_device_is_compatible(dt_node, "fsl,qman-portal-3.1.0") ||
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of_device_is_compatible(dt_node, "fsl,qman-portal-3.1.1") ||
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of_device_is_compatible(dt_node, "fsl,qman-portal-3.1.2") ||
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of_device_is_compatible(dt_node, "fsl,qman-portal-3.1.3"))
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qman_ip_rev = QMAN_REV31;
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else if (of_device_is_compatible(dt_node, "fsl,qman-portal-3.2.0") ||
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of_device_is_compatible(dt_node, "fsl,qman-portal-3.2.1"))
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qman_ip_rev = QMAN_REV32;
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else
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qman_ip_rev = QMAN_REV11;
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if (!qman_ip_rev) {
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pr_err("Unknown qman portal version\n");
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return -ENODEV;
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}
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if ((qman_ip_rev & 0xFF00) >= QMAN_REV30) {
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qm_channel_pool1 = QMAN_CHANNEL_POOL1_REV3;
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qm_channel_caam = QMAN_CHANNEL_CAAM_REV3;
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qm_channel_pme = QMAN_CHANNEL_PME_REV3;
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}
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dt_node = of_find_compatible_node(NULL, NULL, "fsl,pool-channel-range");
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if (!dt_node) {
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pr_err("No qman pool channel range available\n");
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return -ENODEV;
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}
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chanid = of_get_property(dt_node, "fsl,pool-channel-range", &lenp);
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if (!chanid) {
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pr_err("Can not get pool-channel-range property\n");
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return -EINVAL;
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}
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/* get ccsr base */
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dt_node = of_find_compatible_node(NULL, NULL, "fsl,qman");
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if (!dt_node) {
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pr_err("No qman device node available\n");
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return -ENODEV;
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}
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qman_addr = of_get_address(dt_node, 0, ®s_size, NULL);
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if (!qman_addr) {
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pr_err("of_get_address cannot return qman address\n");
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return -EINVAL;
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}
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phys_addr = of_translate_address(dt_node, qman_addr);
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if (!phys_addr) {
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pr_err("of_translate_address failed\n");
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return -EINVAL;
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}
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ccsr_map_fd = open("/dev/mem", O_RDWR);
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if (unlikely(ccsr_map_fd < 0)) {
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pr_err("Can not open /dev/mem for qman ccsr map\n");
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return ccsr_map_fd;
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}
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qman_ccsr_map = mmap(NULL, regs_size, PROT_READ | PROT_WRITE,
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MAP_SHARED, ccsr_map_fd, phys_addr);
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if (qman_ccsr_map == MAP_FAILED) {
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pr_err("Can not map qman ccsr base\n");
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return -EINVAL;
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}
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clk = of_get_property(dt_node, "clock-frequency", NULL);
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if (!clk)
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pr_warn("Can't find Qman clock frequency\n");
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else
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qman_clk = be32_to_cpu(*clk);
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return ret;
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}
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303
drivers/bus/dpaa/base/qbman/qman_priv.h
Normal file
303
drivers/bus/dpaa/base/qbman/qman_priv.h
Normal file
@ -0,0 +1,303 @@
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/*-
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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*
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* BSD LICENSE
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*
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* Copyright 2008-2016 Freescale Semiconductor Inc.
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* Copyright 2017 NXP.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of the above-listed copyright holders nor the
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* names of any contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* GPL LICENSE SUMMARY
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*
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* ALTERNATIVELY, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") as published by the Free Software
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* Foundation, either version 2 of that License or (at your option) any
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* later version.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __QMAN_PRIV_H
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#define __QMAN_PRIV_H
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#include "dpaa_sys.h"
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#include <fsl_qman.h>
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/* Congestion Groups */
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/*
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* This wrapper represents a bit-array for the state of the 256 QMan congestion
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* groups. Is also used as a *mask* for congestion groups, eg. so we ignore
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* those that don't concern us. We harness the structure and accessor details
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* already used in the management command to query congestion groups.
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*/
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struct qman_cgrs {
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struct __qm_mcr_querycongestion q;
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};
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static inline void qman_cgrs_init(struct qman_cgrs *c)
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{
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memset(c, 0, sizeof(*c));
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}
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static inline void qman_cgrs_fill(struct qman_cgrs *c)
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{
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memset(c, 0xff, sizeof(*c));
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}
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static inline int qman_cgrs_get(struct qman_cgrs *c, int num)
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{
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return QM_MCR_QUERYCONGESTION(&c->q, num);
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}
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static inline void qman_cgrs_set(struct qman_cgrs *c, int num)
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{
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c->q.state[__CGR_WORD(num)] |= (0x80000000 >> __CGR_SHIFT(num));
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}
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static inline void qman_cgrs_unset(struct qman_cgrs *c, int num)
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{
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c->q.state[__CGR_WORD(num)] &= ~(0x80000000 >> __CGR_SHIFT(num));
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}
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static inline int qman_cgrs_next(struct qman_cgrs *c, int num)
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{
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while ((++num < (int)__CGR_NUM) && !qman_cgrs_get(c, num))
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;
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return num;
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}
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static inline void qman_cgrs_cp(struct qman_cgrs *dest,
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const struct qman_cgrs *src)
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{
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memcpy(dest, src, sizeof(*dest));
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}
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static inline void qman_cgrs_and(struct qman_cgrs *dest,
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const struct qman_cgrs *a,
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const struct qman_cgrs *b)
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{
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int ret;
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u32 *_d = dest->q.state;
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const u32 *_a = a->q.state;
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const u32 *_b = b->q.state;
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for (ret = 0; ret < 8; ret++)
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*(_d++) = *(_a++) & *(_b++);
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}
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static inline void qman_cgrs_xor(struct qman_cgrs *dest,
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const struct qman_cgrs *a,
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const struct qman_cgrs *b)
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{
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int ret;
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u32 *_d = dest->q.state;
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const u32 *_a = a->q.state;
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const u32 *_b = b->q.state;
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for (ret = 0; ret < 8; ret++)
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*(_d++) = *(_a++) ^ *(_b++);
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}
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/* used by CCSR and portal interrupt code */
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enum qm_isr_reg {
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qm_isr_status = 0,
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qm_isr_enable = 1,
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qm_isr_disable = 2,
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qm_isr_inhibit = 3
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};
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struct qm_portal_config {
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/*
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* Corenet portal addresses;
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* [0]==cache-enabled, [1]==cache-inhibited.
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*/
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void __iomem *addr_virt[2];
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struct device_node *node;
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/* Allow these to be joined in lists */
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struct list_head list;
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/* User-visible portal configuration settings */
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/* If the caller enables DQRR stashing (and thus wishes to operate the
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* portal from only one cpu), this is the logical CPU that the portal
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* will stash to. Whether stashing is enabled or not, this setting is
|
||||
* also used for any "core-affine" portals, ie. default portals
|
||||
* associated to the corresponding cpu. -1 implies that there is no
|
||||
* core affinity configured.
|
||||
*/
|
||||
int cpu;
|
||||
/* portal interrupt line */
|
||||
int irq;
|
||||
/* the unique index of this portal */
|
||||
u32 index;
|
||||
/* Is this portal shared? (If so, it has coarser locking and demuxes
|
||||
* processing on behalf of other CPUs.).
|
||||
*/
|
||||
int is_shared;
|
||||
/* The portal's dedicated channel id, use this value for initialising
|
||||
* frame queues to target this portal when scheduled.
|
||||
*/
|
||||
u16 channel;
|
||||
/* A mask of which pool channels this portal has dequeue access to
|
||||
* (using QM_SDQCR_CHANNELS_POOL(n) for the bitmask).
|
||||
*/
|
||||
u32 pools;
|
||||
|
||||
};
|
||||
|
||||
/* Revision info (for errata and feature handling) */
|
||||
#define QMAN_REV11 0x0101
|
||||
#define QMAN_REV12 0x0102
|
||||
#define QMAN_REV20 0x0200
|
||||
#define QMAN_REV30 0x0300
|
||||
#define QMAN_REV31 0x0301
|
||||
#define QMAN_REV32 0x0302
|
||||
extern u16 qman_ip_rev; /* 0 if uninitialised, otherwise QMAN_REVx */
|
||||
extern u32 qman_clk;
|
||||
|
||||
int qm_set_wpm(int wpm);
|
||||
int qm_get_wpm(int *wpm);
|
||||
|
||||
struct qman_portal *qman_create_affine_portal(
|
||||
const struct qm_portal_config *config,
|
||||
const struct qman_cgrs *cgrs);
|
||||
const struct qm_portal_config *qman_destroy_affine_portal(void);
|
||||
|
||||
struct qm_portal_config *qm_get_unused_portal(void);
|
||||
struct qm_portal_config *qm_get_unused_portal_idx(uint32_t idx);
|
||||
|
||||
void qm_put_unused_portal(struct qm_portal_config *pcfg);
|
||||
void qm_set_liodns(struct qm_portal_config *pcfg);
|
||||
|
||||
/* This CGR feature is supported by h/w and required by unit-tests and the
|
||||
* debugfs hooks, so is implemented in the driver. However it allows an explicit
|
||||
* corruption of h/w fields by s/w that are usually incorruptible (because the
|
||||
* counters are usually maintained entirely within h/w). As such, we declare
|
||||
* this API internally.
|
||||
*/
|
||||
int qman_testwrite_cgr(struct qman_cgr *cgr, u64 i_bcnt,
|
||||
struct qm_mcr_cgrtestwrite *result);
|
||||
|
||||
/* QMan s/w corenet portal, low-level i/face */
|
||||
|
||||
/*
|
||||
* For Choose one SOURCE. Choose one COUNT. Choose one
|
||||
* dequeue TYPE. Choose TOKEN (8-bit).
|
||||
* If SOURCE == CHANNELS,
|
||||
* Choose CHANNELS_DEDICATED and/or CHANNELS_POOL(n).
|
||||
* You can choose DEDICATED_PRECEDENCE if the portal channel should have
|
||||
* priority.
|
||||
* If SOURCE == SPECIFICWQ,
|
||||
* Either select the work-queue ID with SPECIFICWQ_WQ(), or select the
|
||||
* channel (SPECIFICWQ_DEDICATED or SPECIFICWQ_POOL()) and specify the
|
||||
* work-queue priority (0-7) with SPECIFICWQ_WQ() - either way, you get the
|
||||
* same value.
|
||||
*/
|
||||
#define QM_SDQCR_SOURCE_CHANNELS 0x0
|
||||
#define QM_SDQCR_SOURCE_SPECIFICWQ 0x40000000
|
||||
#define QM_SDQCR_COUNT_EXACT1 0x0
|
||||
#define QM_SDQCR_COUNT_UPTO3 0x20000000
|
||||
#define QM_SDQCR_DEDICATED_PRECEDENCE 0x10000000
|
||||
#define QM_SDQCR_TYPE_MASK 0x03000000
|
||||
#define QM_SDQCR_TYPE_NULL 0x0
|
||||
#define QM_SDQCR_TYPE_PRIO_QOS 0x01000000
|
||||
#define QM_SDQCR_TYPE_ACTIVE_QOS 0x02000000
|
||||
#define QM_SDQCR_TYPE_ACTIVE 0x03000000
|
||||
#define QM_SDQCR_TOKEN_MASK 0x00ff0000
|
||||
#define QM_SDQCR_TOKEN_SET(v) (((v) & 0xff) << 16)
|
||||
#define QM_SDQCR_TOKEN_GET(v) (((v) >> 16) & 0xff)
|
||||
#define QM_SDQCR_CHANNELS_DEDICATED 0x00008000
|
||||
#define QM_SDQCR_SPECIFICWQ_MASK 0x000000f7
|
||||
#define QM_SDQCR_SPECIFICWQ_DEDICATED 0x00000000
|
||||
#define QM_SDQCR_SPECIFICWQ_POOL(n) ((n) << 4)
|
||||
#define QM_SDQCR_SPECIFICWQ_WQ(n) (n)
|
||||
|
||||
#define QM_VDQCR_FQID_MASK 0x00ffffff
|
||||
#define QM_VDQCR_FQID(n) ((n) & QM_VDQCR_FQID_MASK)
|
||||
|
||||
#define QM_EQCR_VERB_VBIT 0x80
|
||||
#define QM_EQCR_VERB_CMD_MASK 0x61 /* but only one value; */
|
||||
#define QM_EQCR_VERB_CMD_ENQUEUE 0x01
|
||||
#define QM_EQCR_VERB_COLOUR_MASK 0x18 /* 4 possible values; */
|
||||
#define QM_EQCR_VERB_COLOUR_GREEN 0x00
|
||||
#define QM_EQCR_VERB_COLOUR_YELLOW 0x08
|
||||
#define QM_EQCR_VERB_COLOUR_RED 0x10
|
||||
#define QM_EQCR_VERB_COLOUR_OVERRIDE 0x18
|
||||
#define QM_EQCR_VERB_INTERRUPT 0x04 /* on command consumption */
|
||||
#define QM_EQCR_VERB_ORP 0x02 /* enable order restoration */
|
||||
#define QM_EQCR_DCA_ENABLE 0x80
|
||||
#define QM_EQCR_DCA_PARK 0x40
|
||||
#define QM_EQCR_DCA_IDXMASK 0x0f /* "DQRR::idx" goes here */
|
||||
#define QM_EQCR_SEQNUM_NESN 0x8000 /* Advance NESN */
|
||||
#define QM_EQCR_SEQNUM_NLIS 0x4000 /* More fragments to come */
|
||||
#define QM_EQCR_SEQNUM_SEQMASK 0x3fff /* sequence number goes here */
|
||||
#define QM_EQCR_FQID_NULL 0 /* eg. for an ORP seqnum hole */
|
||||
|
||||
#define QM_MCC_VERB_VBIT 0x80
|
||||
#define QM_MCC_VERB_MASK 0x7f /* where the verb contains; */
|
||||
#define QM_MCC_VERB_INITFQ_PARKED 0x40
|
||||
#define QM_MCC_VERB_INITFQ_SCHED 0x41
|
||||
#define QM_MCC_VERB_QUERYFQ 0x44
|
||||
#define QM_MCC_VERB_QUERYFQ_NP 0x45 /* "non-programmable" fields */
|
||||
#define QM_MCC_VERB_QUERYWQ 0x46
|
||||
#define QM_MCC_VERB_QUERYWQ_DEDICATED 0x47
|
||||
#define QM_MCC_VERB_ALTER_SCHED 0x48 /* Schedule FQ */
|
||||
#define QM_MCC_VERB_ALTER_FE 0x49 /* Force Eligible FQ */
|
||||
#define QM_MCC_VERB_ALTER_RETIRE 0x4a /* Retire FQ */
|
||||
#define QM_MCC_VERB_ALTER_OOS 0x4b /* Take FQ out of service */
|
||||
#define QM_MCC_VERB_ALTER_FQXON 0x4d /* FQ XON */
|
||||
#define QM_MCC_VERB_ALTER_FQXOFF 0x4e /* FQ XOFF */
|
||||
#define QM_MCC_VERB_INITCGR 0x50
|
||||
#define QM_MCC_VERB_MODIFYCGR 0x51
|
||||
#define QM_MCC_VERB_CGRTESTWRITE 0x52
|
||||
#define QM_MCC_VERB_QUERYCGR 0x58
|
||||
#define QM_MCC_VERB_QUERYCONGESTION 0x59
|
||||
|
||||
/*
|
||||
* Used by all portal interrupt registers except 'inhibit'
|
||||
* Channels with frame availability
|
||||
*/
|
||||
#define QM_PIRQ_DQAVAIL 0x0000ffff
|
||||
|
||||
/* The DQAVAIL interrupt fields break down into these bits; */
|
||||
#define QM_DQAVAIL_PORTAL 0x8000 /* Portal channel */
|
||||
#define QM_DQAVAIL_POOL(n) (0x8000 >> (n)) /* Pool channel, n==[1..15] */
|
||||
#define QM_DQAVAIL_MASK 0xffff
|
||||
/* This mask contains all the "irqsource" bits visible to API users */
|
||||
#define QM_PIRQ_VISIBLE (QM_PIRQ_SLOW | QM_PIRQ_DQRI)
|
||||
|
||||
/* These are qm_<reg>_<verb>(). So for example, qm_disable_write() means "write
|
||||
* the disable register" rather than "disable the ability to write".
|
||||
*/
|
||||
#define qm_isr_status_read(qm) __qm_isr_read(qm, qm_isr_status)
|
||||
#define qm_isr_status_clear(qm, m) __qm_isr_write(qm, qm_isr_status, m)
|
||||
#define qm_isr_enable_read(qm) __qm_isr_read(qm, qm_isr_enable)
|
||||
#define qm_isr_enable_write(qm, v) __qm_isr_write(qm, qm_isr_enable, v)
|
||||
#define qm_isr_disable_read(qm) __qm_isr_read(qm, qm_isr_disable)
|
||||
#define qm_isr_disable_write(qm, v) __qm_isr_write(qm, qm_isr_disable, v)
|
||||
/* TODO: unfortunate name-clash here, reword? */
|
||||
#define qm_isr_inhibit(qm) __qm_isr_write(qm, qm_isr_inhibit, 1)
|
||||
#define qm_isr_uninhibit(qm) __qm_isr_write(qm, qm_isr_inhibit, 0)
|
||||
|
||||
#define QMAN_PORTAL_IRQ_PATH "/dev/fsl-usdpaa-irq"
|
||||
|
||||
#endif /* _QMAN_PRIV_H */
|
||||
1254
drivers/bus/dpaa/include/fsl_qman.h
Normal file
1254
drivers/bus/dpaa/include/fsl_qman.h
Normal file
File diff suppressed because it is too large
Load Diff
@ -47,6 +47,10 @@
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Thread-entry/exit hooks; */
|
||||
int qman_thread_init(void);
|
||||
int qman_thread_finish(void);
|
||||
|
||||
#define QBMAN_ANY_PORTAL_IDX 0xffffffff
|
||||
|
||||
/* Obtain and free raw (unitialized) portals */
|
||||
@ -81,6 +85,15 @@ int qman_free_raw_portal(struct dpaa_raw_portal *portal);
|
||||
int bman_allocate_raw_portal(struct dpaa_raw_portal *portal);
|
||||
int bman_free_raw_portal(struct dpaa_raw_portal *portal);
|
||||
|
||||
/* Post-process interrupts. NB, the kernel IRQ handler disables the interrupt
|
||||
* line before notifying us, and this post-processing re-enables it once
|
||||
* processing is complete. As such, it is essential to call this before going
|
||||
* into another blocking read/select/poll.
|
||||
*/
|
||||
void qman_thread_irq(void);
|
||||
|
||||
/* Global setup */
|
||||
int qman_global_init(void);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user