compress/mlx5: add data-path functions
Add implementation for the next compress data-path functions: - dequeue_burst - enqueue_burst Add the next operation for starting \ stopping data-path: - dev_stop - dev_close Each compress API enqueued operation is translated to a WQE. Once WQE is done, the HW sends CQE to the CQ, when SW see the CQE the operation will be updated and dequeued. Signed-off-by: Matan Azrad <matan@nvidia.com> Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
This commit is contained in:
Matan Azrad
Akhil Goyal
parent
0165bccdb4
commit
f8c97babc9
@ -348,10 +348,23 @@ mlx5_compress_xform_create(struct rte_compressdev *dev,
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return -ENOTSUP;
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}
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static void
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mlx5_compress_dev_stop(struct rte_compressdev *dev)
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{
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RTE_SET_USED(dev);
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}
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static int
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mlx5_compress_dev_start(struct rte_compressdev *dev)
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{
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RTE_SET_USED(dev);
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return 0;
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}
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static struct rte_compressdev_ops mlx5_compress_ops = {
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.dev_configure = mlx5_compress_dev_configure,
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.dev_start = NULL,
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.dev_stop = NULL,
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.dev_start = mlx5_compress_dev_start,
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.dev_stop = mlx5_compress_dev_stop,
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.dev_close = mlx5_compress_dev_close,
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.dev_infos_get = mlx5_compress_dev_info_get,
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.stats_get = NULL,
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@ -364,6 +377,203 @@ static struct rte_compressdev_ops mlx5_compress_ops = {
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.stream_free = NULL,
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};
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static __rte_always_inline uint32_t
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mlx5_compress_dseg_set(struct mlx5_compress_qp *qp,
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volatile struct mlx5_wqe_dseg *restrict dseg,
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struct rte_mbuf *restrict mbuf,
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uint32_t offset, uint32_t len)
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{
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uintptr_t addr = rte_pktmbuf_mtod_offset(mbuf, uintptr_t, offset);
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dseg->bcount = rte_cpu_to_be_32(len);
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dseg->lkey = mlx5_mr_addr2mr_bh(qp->priv->pd, 0, &qp->priv->mr_scache,
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&qp->mr_ctrl, addr,
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!!(mbuf->ol_flags & EXT_ATTACHED_MBUF));
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dseg->pbuf = rte_cpu_to_be_64(addr);
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return dseg->lkey;
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}
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static uint16_t
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mlx5_compress_enqueue_burst(void *queue_pair, struct rte_comp_op **ops,
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uint16_t nb_ops)
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{
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struct mlx5_compress_qp *qp = queue_pair;
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volatile struct mlx5_gga_wqe *wqes = (volatile struct mlx5_gga_wqe *)
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qp->sq.wqes, *wqe;
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struct mlx5_compress_xform *xform;
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struct rte_comp_op *op;
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uint16_t mask = qp->entries_n - 1;
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uint16_t remain = qp->entries_n - (qp->pi - qp->ci);
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uint16_t idx;
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bool invalid;
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if (remain < nb_ops)
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nb_ops = remain;
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else
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remain = nb_ops;
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if (unlikely(remain == 0))
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return 0;
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do {
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idx = qp->pi & mask;
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wqe = &wqes[idx];
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rte_prefetch0(&wqes[(qp->pi + 1) & mask]);
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op = *ops++;
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xform = op->private_xform;
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/*
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* Check operation arguments and error cases:
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* - Operation type must be state-less.
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* - Compress operation flush flag must be FULL or FINAL.
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* - Source and destination buffers must be mapped internally.
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*/
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invalid = op->op_type != RTE_COMP_OP_STATELESS ||
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(xform->type == RTE_COMP_COMPRESS &&
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op->flush_flag < RTE_COMP_FLUSH_FULL);
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if (unlikely(invalid ||
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(mlx5_compress_dseg_set(qp, &wqe->gather,
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op->m_src,
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op->src.offset,
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op->src.length) ==
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UINT32_MAX) ||
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(mlx5_compress_dseg_set(qp, &wqe->scatter,
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op->m_dst,
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op->dst.offset,
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rte_pktmbuf_pkt_len(op->m_dst) -
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op->dst.offset) ==
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UINT32_MAX))) {
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op->status = invalid ? RTE_COMP_OP_STATUS_INVALID_ARGS :
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RTE_COMP_OP_STATUS_ERROR;
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nb_ops -= remain;
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if (unlikely(nb_ops == 0))
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return 0;
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break;
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}
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wqe->gga_ctrl1 = xform->gga_ctrl1;
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wqe->opcode = rte_cpu_to_be_32(xform->opcode + (qp->pi << 8));
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qp->ops[idx] = op;
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qp->pi++;
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} while (--remain);
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rte_io_wmb();
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qp->sq.db_rec[MLX5_SND_DBR] = rte_cpu_to_be_32(qp->pi);
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rte_wmb();
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*qp->uar_addr = *(volatile uint64_t *)wqe; /* Assume 64 bit ARCH.*/
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rte_wmb();
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return nb_ops;
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}
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static void
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mlx5_compress_dump_err_objs(volatile uint32_t *cqe, volatile uint32_t *wqe,
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volatile uint32_t *opaq)
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{
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size_t i;
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DRV_LOG(ERR, "Error cqe:");
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for (i = 0; i < sizeof(struct mlx5_err_cqe) >> 2; i += 4)
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DRV_LOG(ERR, "%08X %08X %08X %08X", cqe[i], cqe[i + 1],
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cqe[i + 2], cqe[i + 3]);
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DRV_LOG(ERR, "\nError wqe:");
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for (i = 0; i < sizeof(struct mlx5_gga_wqe) >> 2; i += 4)
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DRV_LOG(ERR, "%08X %08X %08X %08X", wqe[i], wqe[i + 1],
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wqe[i + 2], wqe[i + 3]);
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DRV_LOG(ERR, "\nError opaq:");
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for (i = 0; i < sizeof(struct mlx5_gga_compress_opaque) >> 2; i += 4)
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DRV_LOG(ERR, "%08X %08X %08X %08X", opaq[i], opaq[i + 1],
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opaq[i + 2], opaq[i + 3]);
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}
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static void
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mlx5_compress_cqe_err_handle(struct mlx5_compress_qp *qp,
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struct rte_comp_op *op)
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{
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const uint32_t idx = qp->ci & (qp->entries_n - 1);
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volatile struct mlx5_err_cqe *cqe = (volatile struct mlx5_err_cqe *)
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&qp->cq.cqes[idx];
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volatile struct mlx5_gga_wqe *wqes = (volatile struct mlx5_gga_wqe *)
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qp->sq.wqes;
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volatile struct mlx5_gga_compress_opaque *opaq = qp->opaque_mr.addr;
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op->status = RTE_COMP_OP_STATUS_ERROR;
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op->consumed = 0;
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op->produced = 0;
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op->output_chksum = 0;
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op->debug_status = rte_be_to_cpu_32(opaq[idx].syndrom) |
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((uint64_t)rte_be_to_cpu_32(cqe->syndrome) << 32);
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mlx5_compress_dump_err_objs((volatile uint32_t *)cqe,
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(volatile uint32_t *)&wqes[idx],
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(volatile uint32_t *)&opaq[idx]);
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}
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static uint16_t
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mlx5_compress_dequeue_burst(void *queue_pair, struct rte_comp_op **ops,
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uint16_t nb_ops)
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{
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struct mlx5_compress_qp *qp = queue_pair;
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volatile struct mlx5_compress_xform *restrict xform;
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volatile struct mlx5_cqe *restrict cqe;
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volatile struct mlx5_gga_compress_opaque *opaq = qp->opaque_mr.addr;
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struct rte_comp_op *restrict op;
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const unsigned int cq_size = qp->entries_n;
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const unsigned int mask = cq_size - 1;
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uint32_t idx;
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uint32_t next_idx = qp->ci & mask;
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const uint16_t max = RTE_MIN((uint16_t)(qp->pi - qp->ci), nb_ops);
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uint16_t i = 0;
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int ret;
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if (unlikely(max == 0))
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return 0;
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do {
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idx = next_idx;
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next_idx = (qp->ci + 1) & mask;
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rte_prefetch0(&qp->cq.cqes[next_idx]);
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rte_prefetch0(qp->ops[next_idx]);
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op = qp->ops[idx];
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cqe = &qp->cq.cqes[idx];
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ret = check_cqe(cqe, cq_size, qp->ci);
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/*
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* Be sure owner read is done before any other cookie field or
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* opaque field.
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*/
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rte_io_rmb();
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if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) {
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if (likely(ret == MLX5_CQE_STATUS_HW_OWN))
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break;
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mlx5_compress_cqe_err_handle(qp, op);
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} else {
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xform = op->private_xform;
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op->status = RTE_COMP_OP_STATUS_SUCCESS;
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op->consumed = op->src.length;
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op->produced = rte_be_to_cpu_32(cqe->byte_cnt);
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MLX5_ASSERT(cqe->byte_cnt ==
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qp->opaque_buf[idx].scattered_length);
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switch (xform->csum_type) {
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case RTE_COMP_CHECKSUM_CRC32:
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op->output_chksum = (uint64_t)rte_be_to_cpu_32
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(opaq[idx].crc32);
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break;
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case RTE_COMP_CHECKSUM_ADLER32:
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op->output_chksum = (uint64_t)rte_be_to_cpu_32
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(opaq[idx].adler32) << 32;
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break;
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case RTE_COMP_CHECKSUM_CRC32_ADLER32:
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op->output_chksum = (uint64_t)rte_be_to_cpu_32
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(opaq[idx].crc32) |
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((uint64_t)rte_be_to_cpu_32
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(opaq[idx].adler32) << 32);
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break;
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default:
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break;
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}
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}
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ops[i++] = op;
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qp->ci++;
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} while (i < max);
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if (likely(i != 0)) {
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rte_io_wmb();
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qp->cq.db_rec[0] = rte_cpu_to_be_32(qp->ci);
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}
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return i;
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}
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static struct ibv_device *
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mlx5_compress_get_ib_device_match(struct rte_pci_addr *addr)
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{
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@ -520,8 +730,8 @@ mlx5_compress_pci_probe(struct rte_pci_driver *pci_drv,
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DRV_LOG(INFO,
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"Compress device %s was created successfully.", ibv->name);
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cdev->dev_ops = &mlx5_compress_ops;
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cdev->dequeue_burst = NULL;
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cdev->enqueue_burst = NULL;
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cdev->dequeue_burst = mlx5_compress_dequeue_burst;
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cdev->enqueue_burst = mlx5_compress_enqueue_burst;
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cdev->feature_flags = RTE_COMPDEV_FF_HW_ACCELERATED;
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priv = cdev->data->dev_private;
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priv->ctx = ctx;
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