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examples/performance-thread: support ARM64

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Updated Makefile to allow compilation for arm64 architecture.

Added necessary arm64 support for lthread.

Fixed minor compilation errors for arm64 compilation.

Tested the apps l3fwd-thread and lthread_pthread_shim on thunderx
and x86_64.

Signed-off-by: Ashwin Sekhar T K <ashwin.sekhar@caviumnetworks.com>
This commit is contained in:
Ashwin Sekhar T K 2017-07-04 01:22:41 -07:00 committed by Thomas Monjalon
parent de88718f63
commit f9599fa054
6 changed files with 262 additions and 3 deletions
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4
examples/performance-thread/Makefile
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@ -38,8 +38,8 @@ RTE_TARGET ?= x86_64-native-linuxapp-gcc
include $(RTE_SDK)/mk/rte.vars.mk
ifneq ($(CONFIG_RTE_ARCH),"x86_64")
$(error This application is only supported for x86_64 targets)
ifeq ($(filter y,$(CONFIG_RTE_ARCH_X86_64) $(CONFIG_RTE_ARCH_ARM64)),)
$(error This application is only supported for x86_64 and arm64 targets)
endif
DIRS-y += l3fwd-thread

90
examples/performance-thread/common/arch/arm64/ctx.c Normal file
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@ -0,0 +1,90 @@
/*
* BSD LICENSE
*
* Copyright (C) Cavium networks Ltd. 2017.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Cavium networks nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <rte_common.h>
#include <ctx.h>
void
ctx_switch(struct ctx *new_ctx __rte_unused, struct ctx *curr_ctx __rte_unused)
{
/* SAVE CURRENT CONTEXT */
asm volatile (
/* Save SP */
"mov x3, sp\n"
"str x3, [x1, #0]\n"
/* Save FP and LR */
"stp x29, x30, [x1, #8]\n"
/* Save Callee Saved Regs x19 - x28 */
"stp x19, x20, [x1, #24]\n"
"stp x21, x22, [x1, #40]\n"
"stp x23, x24, [x1, #56]\n"
"stp x25, x26, [x1, #72]\n"
"stp x27, x28, [x1, #88]\n"
/*
* Save bottom 64-bits of Callee Saved
* SIMD Regs v8 - v15
*/
"stp d8, d9, [x1, #104]\n"
"stp d10, d11, [x1, #120]\n"
"stp d12, d13, [x1, #136]\n"
"stp d14, d15, [x1, #152]\n"
);
/* RESTORE NEW CONTEXT */
asm volatile (
/* Restore SP */
"ldr x3, [x0, #0]\n"
"mov sp, x3\n"
/* Restore FP and LR */
"ldp x29, x30, [x0, #8]\n"
/* Restore Callee Saved Regs x19 - x28 */
"ldp x19, x20, [x0, #24]\n"
"ldp x21, x22, [x0, #40]\n"
"ldp x23, x24, [x0, #56]\n"
"ldp x25, x26, [x0, #72]\n"
"ldp x27, x28, [x0, #88]\n"
/*
* Restore bottom 64-bits of Callee Saved
* SIMD Regs v8 - v15
*/
"ldp d8, d9, [x0, #104]\n"
"ldp d10, d11, [x0, #120]\n"
"ldp d12, d13, [x0, #136]\n"
"ldp d14, d15, [x0, #152]\n"
);
}

83
examples/performance-thread/common/arch/arm64/ctx.h Normal file
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@ -0,0 +1,83 @@
/*
* BSD LICENSE
*
* Copyright (C) Cavium networks Ltd. 2017.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Cavium networks nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef CTX_H
#define CTX_H
#ifdef __cplusplus
extern "C" {
#endif
/*
* CPU context registers
*/
struct ctx {
void *sp; /* 0 */
void *fp; /* 8 */
void *lr; /* 16 */
/* Callee Saved Generic Registers */
void *r19; /* 24 */
void *r20; /* 32 */
void *r21; /* 40 */
void *r22; /* 48 */
void *r23; /* 56 */
void *r24; /* 64 */
void *r25; /* 72 */
void *r26; /* 80 */
void *r27; /* 88 */
void *r28; /* 96 */
/*
* Callee Saved SIMD Registers. Only the bottom 64-bits
* of these registers needs to be saved.
*/
void *v8; /* 104 */
void *v9; /* 112 */
void *v10; /* 120 */
void *v11; /* 128 */
void *v12; /* 136 */
void *v13; /* 144 */
void *v14; /* 152 */
void *v15; /* 160 */
};
void
ctx_switch(struct ctx *new_ctx, struct ctx *curr_ctx);
#ifdef __cplusplus
}
#endif
#endif /* RTE_CTX_H_ */

84
examples/performance-thread/common/arch/arm64/stack.h Normal file
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@ -0,0 +1,84 @@
/*
* BSD LICENSE
*
* Copyright (C) Cavium networks Ltd. 2017.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Cavium networks nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef STACK_H
#define STACK_H
#ifdef __cplusplus
extern "C" {
#endif
#include "lthread_int.h"
/*
* Sets up the initial stack for the lthread.
*/
static inline void
arch_set_stack(struct lthread *lt, void *func)
{
void **stack_top = (void *)((char *)(lt->stack) + lt->stack_size);
/*
* Align stack_top to 16 bytes. Arm64 has the constraint that the
* stack pointer must always be quad-word aligned.
*/
stack_top = (void **)(((unsigned long)(stack_top)) & ~0xfUL);
/*
* First Stack Frame
*/
stack_top[0] = NULL;
stack_top[-1] = NULL;
/*
* Initialize the context
*/
lt->ctx.fp = &stack_top[-1];
lt->ctx.sp = &stack_top[-2];
/*
* Here only the address of _lthread_exec is saved as the link
* register value. The argument to _lthread_exec i.e the address of
* the lthread struct is not saved. This is because the first
* argument to ctx_switch is the address of the new context,
* which also happens to be the address of required lthread struct.
* So while returning from ctx_switch into _thread_exec, parameter
* register x0 will always contain the required value.
*/
lt->ctx.lr = func;
}
#ifdef __cplusplus
}
#endif
#endif /* STACK_H_ */

2
examples/performance-thread/common/common.mk
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@ -39,6 +39,8 @@ MKFILE_PATH=$(abspath $(dir $(lastword $(MAKEFILE_LIST))))
ifeq ($(CONFIG_RTE_ARCH_X86_64),y)
ARCH_PATH += $(MKFILE_PATH)/arch/x86
else ifeq ($(CONFIG_RTE_ARCH_ARM64),y)
ARCH_PATH += $(MKFILE_PATH)/arch/arm64
endif
VPATH := $(MKFILE_PATH) $(ARCH_PATH)

2
examples/performance-thread/l3fwd-thread/main.c
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@ -222,7 +222,7 @@ static uint16_t nb_txd = RTE_TEST_TX_DESC_DEFAULT;
static uint64_t dest_eth_addr[RTE_MAX_ETHPORTS];
static struct ether_addr ports_eth_addr[RTE_MAX_ETHPORTS];
static __m128i val_eth[RTE_MAX_ETHPORTS];
static xmm_t val_eth[RTE_MAX_ETHPORTS];
/* replace first 12B of the ethernet header. */
#define MASK_ETH 0x3f