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net/mlx5: replace memory barrier type

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The reason for the requirement of a barrier between the txq writes
and the doorbell record writes is to avoid a case where the device
reads the doorbell record's new value before the txq writes are flushed
to memory.

The current use of rte_wmb is not necessary, and can be replaced by
rte_io_wmb which is more relaxed.

Replacing the rte_wmb is also expected to improve the throughput.

Signed-off-by: Shahaf Shuler <shahafs@mellanox.com>
Signed-off-by: Yongseok Koh <yskoh@mellanox.com>
Signed-off-by: Alexander Solganik <solganik@gmail.com>
Signed-off-by: Sagi Grimberg <sagi@grimberg.me>
Acked-by: Nelio Laranjeiro <nelio.laranjeiro@6wind.com>
This commit is contained in:
Shahaf Shuler 2017-08-27 09:47:08 +03:00 committed by Ferruh Yigit
parent ef86e67ad5
commit f9fbd2b3ad
1 changed files with 1 additions and 1 deletions
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drivers/net/mlx5/mlx5_rxtx.h
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@ -605,7 +605,7 @@ mlx5_tx_dbrec(struct txq *txq, volatile struct mlx5_wqe *wqe)
uint64_t *dst = (uint64_t *)((uintptr_t)txq->bf_reg); uint64_t *dst = (uint64_t *)((uintptr_t)txq->bf_reg);
volatile uint64_t *src = ((volatile uint64_t *)wqe); volatile uint64_t *src = ((volatile uint64_t *)wqe);
rte_wmb(); rte_io_wmb();
*txq->qp_db = htonl(txq->wqe_ci); *txq->qp_db = htonl(txq->wqe_ci);
/* Ensure ordering between DB record and BF copy. */ /* Ensure ordering between DB record and BF copy. */
rte_wmb(); rte_wmb();