net/octeontx2: add devargs parsing functions
add various devargs command line options supported by this driver. Signed-off-by: Jerin Jacob <jerinj@marvell.com> Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com> Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com> Signed-off-by: Kiran Kumar K <kirankumark@marvell.com> Signed-off-by: Vamsi Attunuru <vattunuru@marvell.com>
This commit is contained in:
Jerin Jacob
Ferruh Yigit
parent
1e3da54631
commit
fb0198b7dc
@ -30,3 +30,70 @@ The following options may be modified in the ``config`` file.
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- ``CONFIG_RTE_LIBRTE_OCTEONTX2_PMD`` (default ``y``)
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Toggle compilation of the ``librte_pmd_octeontx2`` driver.
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Runtime Config Options
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----------------------
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- ``HW offload ptype parsing disable`` (default ``0``)
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Packet type parsing is HW offloaded by default and this feature may be toggled
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using ``ptype_disable`` ``devargs`` parameter.
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- ``Rx&Tx scalar mode enable`` (default ``0``)
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Ethdev supports both scalar and vector mode, it may be selected at runtime
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using ``scalar_enable`` ``devargs`` parameter.
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- ``RSS reta size`` (default ``64``)
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RSS redirection table size may be configured during runtime using ``reta_size``
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``devargs`` parameter.
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For example::
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-w 0002:02:00.0,reta_size=256
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With the above configuration, reta table of size 256 is populated.
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- ``Flow priority levels`` (default ``3``)
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RTE Flow priority levels can be configured during runtime using
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``flow_max_priority`` ``devargs`` parameter.
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For example::
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-w 0002:02:00.0,flow_max_priority=10
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With the above configuration, priority level was set to 10 (0-9). Max
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priority level supported is 32.
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- ``Reserve Flow entries`` (default ``8``)
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RTE flow entries can be pre allocated and the size of pre allocation can be
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selected runtime using ``flow_prealloc_size`` ``devargs`` parameter.
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For example::
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-w 0002:02:00.0,flow_prealloc_size=4
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With the above configuration, pre alloc size was set to 4. Max pre alloc
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size supported is 32.
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- ``Max SQB buffer count`` (default ``512``)
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Send queue descriptor buffer count may be limited during runtime using
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``max_sqb_count`` ``devargs`` parameter.
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For example::
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-w 0002:02:00.0,max_sqb_count=64
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With the above configuration, each send queue's decscriptor buffer count is
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limited to a maximum of 64 buffers.
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.. note::
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Above devarg parameters are configurable per device, user needs to pass the
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parameters to all the PCIe devices if application requires to configure on
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all the ethdev ports.
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@ -32,9 +32,10 @@ LIBABIVER := 1
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#
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SRCS-$(CONFIG_RTE_LIBRTE_OCTEONTX2_PMD) += \
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otx2_mac.c \
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otx2_ethdev.c
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otx2_ethdev.c \
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otx2_ethdev_devargs.c
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LDLIBS += -lrte_common_octeontx2 -lrte_mempool_octeontx2 -lrte_eal
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LDLIBS += -lrte_ethdev -lrte_bus_pci
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LDLIBS += -lrte_ethdev -lrte_bus_pci -lrte_kvargs
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include $(RTE_SDK)/mk/rte.lib.mk
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@ -5,6 +5,7 @@
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sources = files(
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'otx2_mac.c',
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'otx2_ethdev.c',
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'otx2_ethdev_devargs.c'
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)
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deps += ['bus_pci', 'common_octeontx2', 'mempool_octeontx2']
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@ -137,6 +137,13 @@ otx2_eth_dev_init(struct rte_eth_dev *eth_dev)
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memset(&dev->otx2_eth_dev_data_start, 0, sizeof(*dev) -
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offsetof(struct otx2_eth_dev, otx2_eth_dev_data_start));
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/* Parse devargs string */
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rc = otx2_ethdev_parse_devargs(eth_dev->device->devargs, dev);
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if (rc) {
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otx2_err("Failed to parse devargs rc=%d", rc);
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goto error;
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}
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if (!dev->mbox_active) {
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/* Initialize the base otx2_dev object
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* only if already present
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@ -9,11 +9,13 @@
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#include <rte_common.h>
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#include <rte_ethdev.h>
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#include <rte_kvargs.h>
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#include "otx2_common.h"
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#include "otx2_dev.h"
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#include "otx2_irq.h"
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#include "otx2_mempool.h"
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#include "otx2_rx.h"
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#define OTX2_ETH_DEV_PMD_VERSION "1.0"
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@ -31,6 +33,10 @@
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/* Used for struct otx2_eth_dev::flags */
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#define OTX2_LINK_CFG_IN_PROGRESS_F BIT_ULL(0)
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#define NIX_MAX_SQB 512
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#define NIX_MIN_SQB 32
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#define NIX_RSS_RETA_SIZE 64
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#define NIX_TX_OFFLOAD_CAPA ( \
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DEV_TX_OFFLOAD_MBUF_FAST_FREE | \
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DEV_TX_OFFLOAD_MT_LOCKFREE | \
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@ -56,6 +62,15 @@
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DEV_RX_OFFLOAD_QINQ_STRIP | \
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DEV_RX_OFFLOAD_TIMESTAMP)
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struct otx2_rss_info {
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uint16_t rss_size;
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};
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struct otx2_npc_flow_info {
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uint16_t flow_prealloc_size;
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uint16_t flow_max_priority;
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};
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struct otx2_eth_dev {
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OTX2_DEV; /* Base class */
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MARKER otx2_eth_dev_data_start;
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@ -72,12 +87,16 @@ struct otx2_eth_dev {
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uint16_t nix_msixoff;
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uintptr_t base;
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uintptr_t lmt_addr;
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uint16_t scalar_ena;
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uint16_t max_sqb_count;
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uint16_t rx_offload_flags; /* Selected Rx offload flags(NIX_RX_*_F) */
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uint64_t rx_offloads;
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uint16_t tx_offload_flags; /* Selected Tx offload flags(NIX_TX_*_F) */
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uint64_t tx_offloads;
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uint64_t rx_offload_capa;
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uint64_t tx_offload_capa;
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struct otx2_rss_info rss_info;
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struct otx2_npc_flow_info npc_flow;
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} __rte_cache_aligned;
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static inline struct otx2_eth_dev *
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@ -96,4 +115,8 @@ int otx2_cgx_mac_addr_set(struct rte_eth_dev *eth_dev,
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int otx2_nix_mac_addr_get(struct rte_eth_dev *eth_dev, uint8_t *addr);
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int otx2_cgx_mac_max_entries_get(struct otx2_eth_dev *dev);
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/* Devargs */
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int otx2_ethdev_parse_devargs(struct rte_devargs *devargs,
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struct otx2_eth_dev *dev);
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#endif /* __OTX2_ETHDEV_H__ */
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165
drivers/net/octeontx2/otx2_ethdev_devargs.c
Normal file
165
drivers/net/octeontx2/otx2_ethdev_devargs.c
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@ -0,0 +1,165 @@
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/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(C) 2019 Marvell International Ltd.
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*/
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#include <inttypes.h>
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#include <math.h>
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#include "otx2_ethdev.h"
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static int
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parse_flow_max_priority(const char *key, const char *value, void *extra_args)
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{
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RTE_SET_USED(key);
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uint16_t val;
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val = atoi(value);
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/* Limit the max priority to 32 */
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if (val < 1 || val > 32)
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return -EINVAL;
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*(uint16_t *)extra_args = val;
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return 0;
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}
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static int
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parse_flow_prealloc_size(const char *key, const char *value, void *extra_args)
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{
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RTE_SET_USED(key);
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uint16_t val;
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val = atoi(value);
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/* Limit the prealloc size to 32 */
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if (val < 1 || val > 32)
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return -EINVAL;
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*(uint16_t *)extra_args = val;
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return 0;
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}
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static int
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parse_reta_size(const char *key, const char *value, void *extra_args)
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{
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RTE_SET_USED(key);
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uint32_t val;
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val = atoi(value);
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if (val <= ETH_RSS_RETA_SIZE_64)
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val = ETH_RSS_RETA_SIZE_64;
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else if (val > ETH_RSS_RETA_SIZE_64 && val <= ETH_RSS_RETA_SIZE_128)
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val = ETH_RSS_RETA_SIZE_128;
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else if (val > ETH_RSS_RETA_SIZE_128 && val <= ETH_RSS_RETA_SIZE_256)
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val = ETH_RSS_RETA_SIZE_256;
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else
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val = NIX_RSS_RETA_SIZE;
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*(uint16_t *)extra_args = val;
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return 0;
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}
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static int
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parse_ptype_flag(const char *key, const char *value, void *extra_args)
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{
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RTE_SET_USED(key);
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uint32_t val;
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val = atoi(value);
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if (val)
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val = 0; /* Disable NIX_RX_OFFLOAD_PTYPE_F */
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*(uint16_t *)extra_args = val;
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return 0;
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}
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static int
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parse_flag(const char *key, const char *value, void *extra_args)
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{
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RTE_SET_USED(key);
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*(uint16_t *)extra_args = atoi(value);
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return 0;
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}
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static int
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parse_sqb_count(const char *key, const char *value, void *extra_args)
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{
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RTE_SET_USED(key);
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uint32_t val;
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val = atoi(value);
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if (val < NIX_MIN_SQB || val > NIX_MAX_SQB)
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return -EINVAL;
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*(uint16_t *)extra_args = val;
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return 0;
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}
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#define OTX2_RSS_RETA_SIZE "reta_size"
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#define OTX2_PTYPE_DISABLE "ptype_disable"
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#define OTX2_SCL_ENABLE "scalar_enable"
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#define OTX2_MAX_SQB_COUNT "max_sqb_count"
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#define OTX2_FLOW_PREALLOC_SIZE "flow_prealloc_size"
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#define OTX2_FLOW_MAX_PRIORITY "flow_max_priority"
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int
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otx2_ethdev_parse_devargs(struct rte_devargs *devargs, struct otx2_eth_dev *dev)
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{
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uint16_t offload_flag = NIX_RX_OFFLOAD_PTYPE_F;
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uint16_t rss_size = NIX_RSS_RETA_SIZE;
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uint16_t sqb_count = NIX_MAX_SQB;
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uint16_t flow_prealloc_size = 8;
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uint16_t flow_max_priority = 3;
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uint16_t scalar_enable = 0;
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struct rte_kvargs *kvlist;
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if (devargs == NULL)
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goto null_devargs;
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kvlist = rte_kvargs_parse(devargs->args, NULL);
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if (kvlist == NULL)
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goto exit;
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rte_kvargs_process(kvlist, OTX2_PTYPE_DISABLE,
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&parse_ptype_flag, &offload_flag);
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rte_kvargs_process(kvlist, OTX2_RSS_RETA_SIZE,
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&parse_reta_size, &rss_size);
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rte_kvargs_process(kvlist, OTX2_SCL_ENABLE,
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&parse_flag, &scalar_enable);
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rte_kvargs_process(kvlist, OTX2_MAX_SQB_COUNT,
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&parse_sqb_count, &sqb_count);
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rte_kvargs_process(kvlist, OTX2_FLOW_PREALLOC_SIZE,
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&parse_flow_prealloc_size, &flow_prealloc_size);
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rte_kvargs_process(kvlist, OTX2_FLOW_MAX_PRIORITY,
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&parse_flow_max_priority, &flow_max_priority);
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rte_kvargs_free(kvlist);
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null_devargs:
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dev->rx_offload_flags = offload_flag;
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dev->scalar_ena = scalar_enable;
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dev->max_sqb_count = sqb_count;
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dev->rss_info.rss_size = rss_size;
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dev->npc_flow.flow_prealloc_size = flow_prealloc_size;
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dev->npc_flow.flow_max_priority = flow_max_priority;
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return 0;
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exit:
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return -EINVAL;
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}
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RTE_PMD_REGISTER_PARAM_STRING(net_octeontx2,
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OTX2_RSS_RETA_SIZE "=<64|128|256>"
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OTX2_PTYPE_DISABLE "=1"
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OTX2_SCL_ENABLE "=1"
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OTX2_MAX_SQB_COUNT "=<32-512>"
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OTX2_FLOW_PREALLOC_SIZE "=<1-32>"
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OTX2_FLOW_MAX_PRIORITY "=<1-32>");
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10
drivers/net/octeontx2/otx2_rx.h
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10
drivers/net/octeontx2/otx2_rx.h
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@ -0,0 +1,10 @@
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/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(C) 2019 Marvell International Ltd.
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*/
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#ifndef __OTX2_RX_H__
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#define __OTX2_RX_H__
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#define NIX_RX_OFFLOAD_PTYPE_F BIT(1)
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#endif /* __OTX2_RX_H__ */
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