i40e/base: support LED blinking with new PHY
This patch adds functions to blink led on devices using a new PHY since MAC registers used in other designs do not work in this device configuration. Signed-off-by: Helin Zhang <helin.zhang@intel.com> Acked-by: Jingjing Wu <jingjing.wu@intel.com> Acked-by: Remy Horton <remy.horton@intel.com>
This commit is contained in:
Helin Zhang
Thomas Monjalon
parent
3db9af65de
commit
fd72a2284a
@ -5969,6 +5969,335 @@ enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
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return status;
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}
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/**
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* i40e_read_phy_register
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* @hw: pointer to the HW structure
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* @page: registers page number
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* @reg: register address in the page
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* @phy_adr: PHY address on MDIO interface
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* @value: PHY register value
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*
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* Reads specified PHY register value
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**/
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enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw,
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u8 page, u16 reg, u8 phy_addr,
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u16 *value)
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{
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enum i40e_status_code status = I40E_ERR_TIMEOUT;
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u32 command = 0;
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u16 retry = 1000;
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u8 port_num = (u8)hw->func_caps.mdio_port_num;
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command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
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(page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
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(phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
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(I40E_MDIO_OPCODE_ADDRESS) |
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(I40E_MDIO_STCODE) |
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(I40E_GLGEN_MSCA_MDICMD_MASK) |
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(I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
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wr32(hw, I40E_GLGEN_MSCA(port_num), command);
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do {
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command = rd32(hw, I40E_GLGEN_MSCA(port_num));
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if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
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status = I40E_SUCCESS;
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break;
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}
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i40e_usec_delay(10);
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retry--;
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} while (retry);
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if (status) {
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i40e_debug(hw, I40E_DEBUG_PHY,
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"PHY: Can't write command to external PHY.\n");
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goto phy_read_end;
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}
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command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
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(phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
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(I40E_MDIO_OPCODE_READ) |
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(I40E_MDIO_STCODE) |
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(I40E_GLGEN_MSCA_MDICMD_MASK) |
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(I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
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status = I40E_ERR_TIMEOUT;
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retry = 1000;
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wr32(hw, I40E_GLGEN_MSCA(port_num), command);
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do {
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command = rd32(hw, I40E_GLGEN_MSCA(port_num));
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if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
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status = I40E_SUCCESS;
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break;
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}
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i40e_usec_delay(10);
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retry--;
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} while (retry);
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if (!status) {
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command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
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*value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
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I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
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} else {
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i40e_debug(hw, I40E_DEBUG_PHY,
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"PHY: Can't read register value from external PHY.\n");
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}
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phy_read_end:
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return status;
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}
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/**
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* i40e_write_phy_register
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* @hw: pointer to the HW structure
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* @page: registers page number
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* @reg: register address in the page
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* @phy_adr: PHY address on MDIO interface
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* @value: PHY register value
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*
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* Writes value to specified PHY register
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**/
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enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw,
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u8 page, u16 reg, u8 phy_addr,
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u16 value)
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{
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enum i40e_status_code status = I40E_ERR_TIMEOUT;
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u32 command = 0;
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u16 retry = 1000;
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u8 port_num = (u8)hw->func_caps.mdio_port_num;
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command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
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(page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
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(phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
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(I40E_MDIO_OPCODE_ADDRESS) |
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(I40E_MDIO_STCODE) |
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(I40E_GLGEN_MSCA_MDICMD_MASK) |
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(I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
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wr32(hw, I40E_GLGEN_MSCA(port_num), command);
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do {
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command = rd32(hw, I40E_GLGEN_MSCA(port_num));
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if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
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status = I40E_SUCCESS;
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break;
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}
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i40e_usec_delay(10);
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retry--;
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} while (retry);
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if (status) {
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i40e_debug(hw, I40E_DEBUG_PHY,
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"PHY: Can't write command to external PHY.\n");
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goto phy_write_end;
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}
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command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
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wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
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command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
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(phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
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(I40E_MDIO_OPCODE_WRITE) |
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(I40E_MDIO_STCODE) |
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(I40E_GLGEN_MSCA_MDICMD_MASK) |
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(I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
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status = I40E_ERR_TIMEOUT;
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retry = 1000;
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wr32(hw, I40E_GLGEN_MSCA(port_num), command);
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do {
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command = rd32(hw, I40E_GLGEN_MSCA(port_num));
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if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
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status = I40E_SUCCESS;
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break;
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}
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i40e_usec_delay(10);
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retry--;
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} while (retry);
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phy_write_end:
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return status;
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}
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/**
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* i40e_get_phy_address
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* @hw: pointer to the HW structure
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* @dev_num: PHY port num that address we want
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* @phy_addr: Returned PHY address
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*
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* Gets PHY address for current port
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**/
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u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
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{
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u8 port_num = (u8)hw->func_caps.mdio_port_num;
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u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
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return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
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}
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/**
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* i40e_blink_phy_led
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* @hw: pointer to the HW structure
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* @time: time how long led will blinks in secs
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* @interval: gap between LED on and off in msecs
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*
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* Blinks PHY link LED
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**/
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enum i40e_status_code i40e_blink_phy_link_led(struct i40e_hw *hw,
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u32 time, u32 interval)
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{
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enum i40e_status_code status = I40E_SUCCESS;
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u32 i;
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u16 led_ctl = 0;
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u16 gpio_led_port;
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u16 led_reg;
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u16 led_addr = I40E_PHY_LED_PROV_REG_1;
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u8 phy_addr = 0;
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u8 port_num;
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i = rd32(hw, I40E_PFGEN_PORTNUM);
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port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
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phy_addr = i40e_get_phy_address(hw, port_num);
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for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
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led_addr++) {
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status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,
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led_addr, phy_addr, &led_reg);
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if (status)
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goto phy_blinking_end;
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led_ctl = led_reg;
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if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
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led_reg = 0;
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status = i40e_write_phy_register(hw,
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I40E_PHY_COM_REG_PAGE,
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led_addr, phy_addr,
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led_reg);
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if (status)
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goto phy_blinking_end;
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break;
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}
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}
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if (time > 0 && interval > 0) {
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for (i = 0; i < time * 1000; i += interval) {
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status = i40e_read_phy_register(hw,
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I40E_PHY_COM_REG_PAGE,
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led_addr, phy_addr,
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&led_reg);
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if (status)
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goto restore_config;
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if (led_reg & I40E_PHY_LED_MANUAL_ON)
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led_reg = 0;
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else
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led_reg = I40E_PHY_LED_MANUAL_ON;
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status = i40e_write_phy_register(hw,
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I40E_PHY_COM_REG_PAGE,
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led_addr, phy_addr,
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led_reg);
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if (status)
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goto restore_config;
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i40e_msec_delay(interval);
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}
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}
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restore_config:
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status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,
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phy_addr, led_ctl);
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phy_blinking_end:
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return status;
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}
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/**
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* i40e_led_get_phy - return current on/off mode
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* @hw: pointer to the hw struct
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* @led_addr: address of led register to use
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* @val: original value of register to use
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*
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**/
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enum i40e_status_code i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
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u16 *val)
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{
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enum i40e_status_code status = I40E_SUCCESS;
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u16 gpio_led_port;
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u8 phy_addr = 0;
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u16 reg_val;
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u16 temp_addr;
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u8 port_num;
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u32 i;
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temp_addr = I40E_PHY_LED_PROV_REG_1;
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i = rd32(hw, I40E_PFGEN_PORTNUM);
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port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
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phy_addr = i40e_get_phy_address(hw, port_num);
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for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
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temp_addr++) {
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status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,
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temp_addr, phy_addr, ®_val);
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if (status)
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return status;
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*val = reg_val;
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if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
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*led_addr = temp_addr;
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break;
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}
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}
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return status;
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}
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/**
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* i40e_led_set_phy
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* @hw: pointer to the HW structure
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* @on: true or false
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* @mode: original val plus bit for set or ignore
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* Set led's on or off when controlled by the PHY
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*
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**/
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enum i40e_status_code i40e_led_set_phy(struct i40e_hw *hw, bool on,
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u16 led_addr, u32 mode)
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{
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enum i40e_status_code status = I40E_SUCCESS;
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u16 led_ctl = 0;
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u16 led_reg = 0;
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u8 phy_addr = 0;
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u8 port_num;
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u32 i;
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i = rd32(hw, I40E_PFGEN_PORTNUM);
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port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
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phy_addr = i40e_get_phy_address(hw, port_num);
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status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,
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phy_addr, &led_reg);
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if (status)
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return status;
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led_ctl = led_reg;
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if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
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led_reg = 0;
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status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE,
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led_addr, phy_addr, led_reg);
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if (status)
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return status;
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}
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status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,
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led_addr, phy_addr, &led_reg);
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if (status)
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goto restore_config;
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if (on)
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led_reg = I40E_PHY_LED_MANUAL_ON;
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else
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led_reg = 0;
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status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE,
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led_addr, phy_addr, led_reg);
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if (status)
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goto restore_config;
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if (mode & I40E_PHY_LED_MODE_ORIG) {
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led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
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status = i40e_write_phy_register(hw,
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I40E_PHY_COM_REG_PAGE,
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led_addr, phy_addr, led_ctl);
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}
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return status;
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restore_config:
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status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,
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phy_addr, led_ctl);
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return status;
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}
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#endif /* PF_DRIVER */
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#ifdef VF_DRIVER
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@ -99,6 +99,12 @@ const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err);
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u32 i40e_led_get(struct i40e_hw *hw);
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void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink);
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enum i40e_status_code i40e_led_set_phy(struct i40e_hw *hw, bool on,
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u16 led_addr, u32 mode);
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enum i40e_status_code i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
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u16 *val);
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enum i40e_status_code i40e_blink_phy_link_led(struct i40e_hw *hw,
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u32 time, u32 interval);
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/* admin send queue commands */
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@ -527,4 +533,11 @@ enum i40e_status_code i40e_aq_get_wake_event_reason(struct i40e_hw *hw,
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u16 *wake_reason,
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struct i40e_asq_cmd_details *cmd_details);
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#endif
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enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw, u8 page,
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u16 reg, u8 phy_addr, u16 *value);
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enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw, u8 page,
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u16 reg, u8 phy_addr, u16 value);
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u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num);
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enum i40e_status_code i40e_blink_phy_link_led(struct i40e_hw *hw,
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u32 time, u32 interval);
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#endif /* _I40E_PROTOTYPE_H_ */
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@ -157,6 +157,22 @@ enum i40e_debug_mask {
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#define I40E_PCI_LINK_SPEED_5000 0x2
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#define I40E_PCI_LINK_SPEED_8000 0x3
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#define I40E_MDIO_STCODE 0
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#define I40E_MDIO_OPCODE_ADDRESS 0
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#define I40E_MDIO_OPCODE_WRITE I40E_MASK(1, \
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I40E_GLGEN_MSCA_OPCODE_SHIFT)
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#define I40E_MDIO_OPCODE_READ_INC_ADDR I40E_MASK(2, \
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I40E_GLGEN_MSCA_OPCODE_SHIFT)
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#define I40E_MDIO_OPCODE_READ I40E_MASK(3, \
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I40E_GLGEN_MSCA_OPCODE_SHIFT)
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#define I40E_PHY_COM_REG_PAGE 0x1E
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#define I40E_PHY_LED_LINK_MODE_MASK 0xF0
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#define I40E_PHY_LED_MANUAL_ON 0x100
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#define I40E_PHY_LED_PROV_REG_1 0xC430
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#define I40E_PHY_LED_MODE_MASK 0xFFFF
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#define I40E_PHY_LED_MODE_ORIG 0x80000000
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/* Memory types */
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enum i40e_memset_type {
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I40E_NONDMA_MEM = 0,
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