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net/octeontx2: enable error and RAS interrupt in configure

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Patch adds routines to set/clear nix lf error & ras interrupt enable
registers. These nix lf error interrupts get triggered if there are
any failures during nix lf configuration. This interrupts are enabled
before any hardware configurations initiated on the allocated nix lf.

Signed-off-by: Vamsi Attunuru <vattunuru@marvell.com>
Acked-by: Andrzej Ostruszka <aostruszka@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
This commit is contained in:
Vamsi Attunuru 2020-04-03 07:50:16 +05:30 committed by Ferruh Yigit
parent 100f699242
commit fdbdf2721c
3 changed files with 34 additions and 6 deletions
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3
drivers/net/octeontx2/otx2_ethdev.c
View File

@ -1666,6 +1666,9 @@ otx2_nix_configure(struct rte_eth_dev *eth_dev)
goto fail_offloads;
}
otx2_nix_err_intr_enb_dis(eth_dev, true);
otx2_nix_ras_intr_enb_dis(eth_dev, true);
if (dev->ptp_en &&
dev->npc_flow.switch_header_type == OTX2_PRIV_FLAGS_HIGIG) {
otx2_err("Both PTP and switch header enabled");

2
drivers/net/octeontx2/otx2_ethdev.h
View File

@ -445,6 +445,8 @@ int oxt2_nix_register_cq_irqs(struct rte_eth_dev *eth_dev);
void otx2_nix_unregister_irqs(struct rte_eth_dev *eth_dev);
void oxt2_nix_unregister_queue_irqs(struct rte_eth_dev *eth_dev);
void oxt2_nix_unregister_cq_irqs(struct rte_eth_dev *eth_dev);
void otx2_nix_err_intr_enb_dis(struct rte_eth_dev *eth_dev, bool enb);
void otx2_nix_ras_intr_enb_dis(struct rte_eth_dev *eth_dev, bool enb);
int otx2_nix_rx_queue_intr_enable(struct rte_eth_dev *eth_dev,
uint16_t rx_queue_id);

35
drivers/net/octeontx2/otx2_ethdev_irq.c
View File

@ -41,11 +41,11 @@ nix_lf_register_err_irq(struct rte_eth_dev *eth_dev)
vec = dev->nix_msixoff + NIX_LF_INT_VEC_ERR_INT;
/* Clear err interrupt */
otx2_write64(~0ull, dev->base + NIX_LF_ERR_INT_ENA_W1C);
otx2_nix_err_intr_enb_dis(eth_dev, false);
/* Set used interrupt vectors */
rc = otx2_register_irq(handle, nix_lf_err_irq, eth_dev, vec);
/* Enable all dev interrupt except for RQ_DISABLED */
otx2_write64(~BIT_ULL(11), dev->base + NIX_LF_ERR_INT_ENA_W1S);
otx2_nix_err_intr_enb_dis(eth_dev, true);
return rc;
}
@ -61,7 +61,7 @@ nix_lf_unregister_err_irq(struct rte_eth_dev *eth_dev)
vec = dev->nix_msixoff + NIX_LF_INT_VEC_ERR_INT;
/* Clear err interrupt */
otx2_write64(~0ull, dev->base + NIX_LF_ERR_INT_ENA_W1C);
otx2_nix_err_intr_enb_dis(eth_dev, false);
otx2_unregister_irq(handle, nix_lf_err_irq, eth_dev, vec);
}
@ -97,11 +97,11 @@ nix_lf_register_ras_irq(struct rte_eth_dev *eth_dev)
vec = dev->nix_msixoff + NIX_LF_INT_VEC_POISON;
/* Clear err interrupt */
otx2_write64(~0ull, dev->base + NIX_LF_RAS_ENA_W1C);
otx2_nix_ras_intr_enb_dis(eth_dev, false);
/* Set used interrupt vectors */
rc = otx2_register_irq(handle, nix_lf_ras_irq, eth_dev, vec);
/* Enable dev interrupt */
otx2_write64(~0ull, dev->base + NIX_LF_RAS_ENA_W1S);
otx2_nix_ras_intr_enb_dis(eth_dev, true);
return rc;
}
@ -117,7 +117,7 @@ nix_lf_unregister_ras_irq(struct rte_eth_dev *eth_dev)
vec = dev->nix_msixoff + NIX_LF_INT_VEC_POISON;
/* Clear err interrupt */
otx2_write64(~0ull, dev->base + NIX_LF_RAS_ENA_W1C);
otx2_nix_ras_intr_enb_dis(eth_dev, false);
otx2_unregister_irq(handle, nix_lf_ras_irq, eth_dev, vec);
}
@ -466,3 +466,26 @@ otx2_nix_rx_queue_intr_disable(struct rte_eth_dev *eth_dev,
return 0;
}
void
otx2_nix_err_intr_enb_dis(struct rte_eth_dev *eth_dev, bool enb)
{
struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
/* Enable all nix lf error interrupts except for RQ_DISABLED */
if (enb)
otx2_write64(~BIT_ULL(11), dev->base + NIX_LF_ERR_INT_ENA_W1S);
else
otx2_write64(~0ull, dev->base + NIX_LF_ERR_INT_ENA_W1C);
}
void
otx2_nix_ras_intr_enb_dis(struct rte_eth_dev *eth_dev, bool enb)
{
struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
if (enb)
otx2_write64(~0ull, dev->base + NIX_LF_RAS_ENA_W1S);
else
otx2_write64(~0ull, dev->base + NIX_LF_RAS_ENA_W1C);
}