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net/mlx5: fix miniCQE configuration for Verbs

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Verbs cannot be used to configure newly introduced miniCQE formats for
Flow Tag and L3/L4 Header compression. Support for these formats has
been added to the DevX configuration only. And the RX queue descriptor
has been updated with the CQE compression format information only as
well. But the datapath relies on this info no matter which method is
used for Rx queues configuration. Set proper CQE compression format
information in the Verbs configuration to fix the miniCQE parsing logic.

Fixes: 54c2d46b160f ("net/mlx5: support flow tag and packet header miniCQEs")
Cc: stable@dpdk.org

Signed-off-by: Alexander Kozyrev <akozyrev@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
This commit is contained in:
Alexander Kozyrev 2021-02-01 17:16:30 +00:00 committed by Ferruh Yigit
parent 3d3f4e6d1a
commit fdc44cdc78
3 changed files with 19 additions and 6 deletions
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6
doc/guides/nics/mlx5.rst
View File

@ -485,13 +485,17 @@ Driver options
A nonzero value enables the compression of CQE on RX side. This feature
allows to save PCI bandwidth and improve performance. Enabled by default.
Different compression formats are supported in order to achieve the best
performance for different traffic patterns. Hash RSS format is the default.
performance for different traffic patterns. Default format depends on
Multi-Packet Rx queue configuration: Hash RSS format is used in case
MPRQ is disabled, Checksum format is used in case MPRQ is enabled.
Specifying 2 as a ``rxq_cqe_comp_en`` value selects Flow Tag format for
better compression rate in case of RTE Flow Mark traffic.
Specifying 3 as a ``rxq_cqe_comp_en`` value selects Checksum format.
Specifying 4 as a ``rxq_cqe_comp_en`` value selects L3/L4 Header format for
better compression rate in case of mixed TCP/UDP and IPv4/IPv6 traffic.
CQE compression format selection requires DevX to be enabled. If there is
no DevX enabled/supported the value is reset to 1 by default.
Supported on:

17
drivers/net/mlx5/linux/mlx5_verbs.c
View File

@ -213,13 +213,22 @@ mlx5_rxq_ibv_cq_create(struct rte_eth_dev *dev, uint16_t idx)
if (priv->config.cqe_comp && !rxq_data->hw_timestamp) {
cq_attr.mlx5.comp_mask |=
MLX5DV_CQ_INIT_ATTR_MASK_COMPRESSED_CQE;
rxq_data->byte_mask = UINT32_MAX;
#ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
cq_attr.mlx5.cqe_comp_res_format =
mlx5_rxq_mprq_enabled(rxq_data) ?
MLX5DV_CQE_RES_FORMAT_CSUM_STRIDX :
MLX5DV_CQE_RES_FORMAT_HASH;
if (mlx5_rxq_mprq_enabled(rxq_data)) {
cq_attr.mlx5.cqe_comp_res_format =
MLX5DV_CQE_RES_FORMAT_CSUM_STRIDX;
rxq_data->mcqe_format =
MLX5_CQE_RESP_FORMAT_CSUM_STRIDX;
} else {
cq_attr.mlx5.cqe_comp_res_format =
MLX5DV_CQE_RES_FORMAT_HASH;
rxq_data->mcqe_format =
MLX5_CQE_RESP_FORMAT_HASH;
}
#else
cq_attr.mlx5.cqe_comp_res_format = MLX5DV_CQE_RES_FORMAT_HASH;
rxq_data->mcqe_format = MLX5_CQE_RESP_FORMAT_HASH;
#endif
/*
* For vectorized Rx, it must not be doubled in order to

2
drivers/net/mlx5/mlx5_rxtx.h
View File

@ -126,7 +126,7 @@ struct mlx5_rxq_data {
unsigned int strd_scatter_en:1; /* Scattered packets from a stride. */
unsigned int lro:1; /* Enable LRO. */
unsigned int dynf_meta:1; /* Dynamic metadata is configured. */
unsigned int mcqe_format:3; /* Dynamic metadata is configured. */
unsigned int mcqe_format:3; /* CQE compression format. */
volatile uint32_t *rq_db;
volatile uint32_t *cq_db;
uint16_t port_id;