raw/ioat: probe idxd PCI
When a matching device is found via PCI probe create a rawdev instance for each queue on the hardware. Use empty self-test function for these devices so that the overall rawdev_autotest does not report failures. Signed-off-by: Bruce Richardson <bruce.richardson@intel.com> Reviewed-by: Kevin Laatz <kevin.laatz@intel.com> Acked-by: Radu Nicolau <radu.nicolau@intel.com>
This commit is contained in:
Bruce Richardson
Thomas Monjalon
parent
01863b9d23
commit
ff06fa2cf3
@ -3,8 +3,10 @@
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*/
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#include <rte_bus_pci.h>
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#include <rte_memzone.h>
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#include "ioat_private.h"
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#include "ioat_spec.h"
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#define IDXD_VENDOR_ID 0x8086
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#define IDXD_DEVICE_ID_SPR 0x0B25
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@ -16,17 +18,246 @@ const struct rte_pci_id pci_id_idxd_map[] = {
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{ .vendor_id = 0, /* sentinel */ },
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};
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static inline int
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idxd_pci_dev_command(struct idxd_rawdev *idxd, enum rte_idxd_cmds command)
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{
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uint8_t err_code;
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uint16_t qid = idxd->qid;
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int i = 0;
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if (command >= idxd_disable_wq && command <= idxd_reset_wq)
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qid = (1 << qid);
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rte_spinlock_lock(&idxd->u.pci->lk);
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idxd->u.pci->regs->cmd = (command << IDXD_CMD_SHIFT) | qid;
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do {
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rte_pause();
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err_code = idxd->u.pci->regs->cmdstatus;
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if (++i >= 1000) {
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IOAT_PMD_ERR("Timeout waiting for command response from HW");
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rte_spinlock_unlock(&idxd->u.pci->lk);
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return err_code;
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}
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} while (idxd->u.pci->regs->cmdstatus & CMDSTATUS_ACTIVE_MASK);
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rte_spinlock_unlock(&idxd->u.pci->lk);
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return err_code & CMDSTATUS_ERR_MASK;
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}
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static int
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idxd_is_wq_enabled(struct idxd_rawdev *idxd)
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{
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uint32_t state = idxd->u.pci->wq_regs[idxd->qid].wqcfg[WQ_STATE_IDX];
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return ((state >> WQ_STATE_SHIFT) & WQ_STATE_MASK) == 0x1;
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}
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static const struct rte_rawdev_ops idxd_pci_ops = {
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.dev_close = idxd_rawdev_close,
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.dev_selftest = idxd_rawdev_test,
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};
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/* each portal uses 4 x 4k pages */
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#define IDXD_PORTAL_SIZE (4096 * 4)
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static int
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init_pci_device(struct rte_pci_device *dev, struct idxd_rawdev *idxd)
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{
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struct idxd_pci_common *pci;
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uint8_t nb_groups, nb_engines, nb_wqs;
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uint16_t grp_offset, wq_offset; /* how far into bar0 the regs are */
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uint16_t wq_size, total_wq_size;
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uint8_t lg2_max_batch, lg2_max_copy_size;
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unsigned int i, err_code;
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pci = malloc(sizeof(*pci));
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if (pci == NULL) {
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IOAT_PMD_ERR("%s: Can't allocate memory", __func__);
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goto err;
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}
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rte_spinlock_init(&pci->lk);
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/* assign the bar registers, and then configure device */
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pci->regs = dev->mem_resource[0].addr;
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grp_offset = (uint16_t)pci->regs->offsets[0];
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pci->grp_regs = RTE_PTR_ADD(pci->regs, grp_offset * 0x100);
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wq_offset = (uint16_t)(pci->regs->offsets[0] >> 16);
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pci->wq_regs = RTE_PTR_ADD(pci->regs, wq_offset * 0x100);
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pci->portals = dev->mem_resource[2].addr;
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/* sanity check device status */
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if (pci->regs->gensts & GENSTS_DEV_STATE_MASK) {
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/* need function-level-reset (FLR) or is enabled */
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IOAT_PMD_ERR("Device status is not disabled, cannot init");
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goto err;
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}
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if (pci->regs->cmdstatus & CMDSTATUS_ACTIVE_MASK) {
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/* command in progress */
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IOAT_PMD_ERR("Device has a command in progress, cannot init");
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goto err;
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}
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/* read basic info about the hardware for use when configuring */
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nb_groups = (uint8_t)pci->regs->grpcap;
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nb_engines = (uint8_t)pci->regs->engcap;
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nb_wqs = (uint8_t)(pci->regs->wqcap >> 16);
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total_wq_size = (uint16_t)pci->regs->wqcap;
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lg2_max_copy_size = (uint8_t)(pci->regs->gencap >> 16) & 0x1F;
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lg2_max_batch = (uint8_t)(pci->regs->gencap >> 21) & 0x0F;
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IOAT_PMD_DEBUG("nb_groups = %u, nb_engines = %u, nb_wqs = %u",
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nb_groups, nb_engines, nb_wqs);
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/* zero out any old config */
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for (i = 0; i < nb_groups; i++) {
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pci->grp_regs[i].grpengcfg = 0;
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pci->grp_regs[i].grpwqcfg[0] = 0;
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}
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for (i = 0; i < nb_wqs; i++)
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pci->wq_regs[i].wqcfg[0] = 0;
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/* put each engine into a separate group to avoid reordering */
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if (nb_groups > nb_engines)
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nb_groups = nb_engines;
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if (nb_groups < nb_engines)
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nb_engines = nb_groups;
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/* assign engines to groups, round-robin style */
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for (i = 0; i < nb_engines; i++) {
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IOAT_PMD_DEBUG("Assigning engine %u to group %u",
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i, i % nb_groups);
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pci->grp_regs[i % nb_groups].grpengcfg |= (1ULL << i);
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}
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/* now do the same for queues and give work slots to each queue */
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wq_size = total_wq_size / nb_wqs;
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IOAT_PMD_DEBUG("Work queue size = %u, max batch = 2^%u, max copy = 2^%u",
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wq_size, lg2_max_batch, lg2_max_copy_size);
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for (i = 0; i < nb_wqs; i++) {
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/* add engine "i" to a group */
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IOAT_PMD_DEBUG("Assigning work queue %u to group %u",
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i, i % nb_groups);
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pci->grp_regs[i % nb_groups].grpwqcfg[0] |= (1ULL << i);
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/* now configure it, in terms of size, max batch, mode */
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pci->wq_regs[i].wqcfg[WQ_SIZE_IDX] = wq_size;
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pci->wq_regs[i].wqcfg[WQ_MODE_IDX] = (1 << WQ_PRIORITY_SHIFT) |
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WQ_MODE_DEDICATED;
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pci->wq_regs[i].wqcfg[WQ_SIZES_IDX] = lg2_max_copy_size |
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(lg2_max_batch << WQ_BATCH_SZ_SHIFT);
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}
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/* dump the group configuration to output */
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for (i = 0; i < nb_groups; i++) {
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IOAT_PMD_DEBUG("## Group %d", i);
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IOAT_PMD_DEBUG(" GRPWQCFG: %"PRIx64, pci->grp_regs[i].grpwqcfg[0]);
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IOAT_PMD_DEBUG(" GRPENGCFG: %"PRIx64, pci->grp_regs[i].grpengcfg);
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IOAT_PMD_DEBUG(" GRPFLAGS: %"PRIx32, pci->grp_regs[i].grpflags);
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}
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idxd->u.pci = pci;
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idxd->max_batches = wq_size;
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/* enable the device itself */
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err_code = idxd_pci_dev_command(idxd, idxd_enable_dev);
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if (err_code) {
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IOAT_PMD_ERR("Error enabling device: code %#x", err_code);
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return err_code;
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}
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IOAT_PMD_DEBUG("IDXD Device enabled OK");
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return nb_wqs;
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err:
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free(pci);
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return -1;
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}
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static int
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idxd_rawdev_probe_pci(struct rte_pci_driver *drv, struct rte_pci_device *dev)
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{
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int ret = 0;
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struct idxd_rawdev idxd = {{0}}; /* Double {} to avoid error on BSD12 */
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uint8_t nb_wqs;
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int qid, ret = 0;
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char name[PCI_PRI_STR_SIZE];
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rte_pci_device_name(&dev->addr, name, sizeof(name));
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IOAT_PMD_INFO("Init %s on NUMA node %d", name, dev->device.numa_node);
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dev->device.driver = &drv->driver;
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return ret;
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ret = init_pci_device(dev, &idxd);
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if (ret < 0) {
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IOAT_PMD_ERR("Error initializing PCI hardware");
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return ret;
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}
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nb_wqs = (uint8_t)ret;
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/* set up one device for each queue */
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for (qid = 0; qid < nb_wqs; qid++) {
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char qname[32];
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/* add the queue number to each device name */
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snprintf(qname, sizeof(qname), "%s-q%d", name, qid);
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idxd.qid = qid;
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idxd.public.portal = RTE_PTR_ADD(idxd.u.pci->portals,
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qid * IDXD_PORTAL_SIZE);
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if (idxd_is_wq_enabled(&idxd))
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IOAT_PMD_ERR("Error, WQ %u seems enabled", qid);
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ret = idxd_rawdev_create(qname, &dev->device,
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&idxd, &idxd_pci_ops);
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if (ret != 0) {
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IOAT_PMD_ERR("Failed to create rawdev %s", name);
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if (qid == 0) /* if no devices using this, free pci */
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free(idxd.u.pci);
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return ret;
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}
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}
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return 0;
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}
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static int
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idxd_rawdev_destroy(const char *name)
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{
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int ret;
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uint8_t err_code;
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struct rte_rawdev *rdev;
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struct idxd_rawdev *idxd;
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if (!name) {
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IOAT_PMD_ERR("Invalid device name");
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return -EINVAL;
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}
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rdev = rte_rawdev_pmd_get_named_dev(name);
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if (!rdev) {
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IOAT_PMD_ERR("Invalid device name (%s)", name);
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return -EINVAL;
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}
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idxd = rdev->dev_private;
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/* disable the device */
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err_code = idxd_pci_dev_command(idxd, idxd_disable_dev);
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if (err_code) {
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IOAT_PMD_ERR("Error disabling device: code %#x", err_code);
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return err_code;
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}
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IOAT_PMD_DEBUG("IDXD Device disabled OK");
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/* free device memory */
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if (rdev->dev_private != NULL) {
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IOAT_PMD_DEBUG("Freeing device driver memory");
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rdev->dev_private = NULL;
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rte_free(idxd->public.batch_ring);
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rte_free(idxd->public.hdl_ring);
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rte_memzone_free(idxd->mz);
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}
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/* rte_rawdev_close is called by pmd_release */
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ret = rte_rawdev_pmd_release(rdev);
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if (ret)
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IOAT_PMD_DEBUG("Device cleanup failed");
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return 0;
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}
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static int
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@ -40,6 +271,8 @@ idxd_rawdev_remove_pci(struct rte_pci_device *dev)
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IOAT_PMD_INFO("Closing %s on NUMA node %d",
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name, dev->device.numa_node);
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ret = idxd_rawdev_destroy(name);
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return ret;
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}
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68
drivers/raw/ioat/ioat_common.c
Normal file
68
drivers/raw/ioat/ioat_common.c
Normal file
@ -0,0 +1,68 @@
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/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2020 Intel Corporation
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*/
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#include <rte_rawdev_pmd.h>
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#include <rte_memzone.h>
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#include <rte_common.h>
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#include "ioat_private.h"
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int
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idxd_rawdev_close(struct rte_rawdev *dev __rte_unused)
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{
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return 0;
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}
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int
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idxd_rawdev_create(const char *name, struct rte_device *dev,
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const struct idxd_rawdev *base_idxd,
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const struct rte_rawdev_ops *ops)
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{
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struct idxd_rawdev *idxd;
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struct rte_rawdev *rawdev = NULL;
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const struct rte_memzone *mz = NULL;
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char mz_name[RTE_MEMZONE_NAMESIZE];
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int ret = 0;
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if (!name) {
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IOAT_PMD_ERR("Invalid name of the device!");
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ret = -EINVAL;
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goto cleanup;
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}
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/* Allocate device structure */
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rawdev = rte_rawdev_pmd_allocate(name, sizeof(struct idxd_rawdev),
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dev->numa_node);
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if (rawdev == NULL) {
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IOAT_PMD_ERR("Unable to allocate raw device");
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ret = -ENOMEM;
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goto cleanup;
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}
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snprintf(mz_name, sizeof(mz_name), "rawdev%u_private", rawdev->dev_id);
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mz = rte_memzone_reserve(mz_name, sizeof(struct idxd_rawdev),
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dev->numa_node, RTE_MEMZONE_IOVA_CONTIG);
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if (mz == NULL) {
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IOAT_PMD_ERR("Unable to reserve memzone for private data\n");
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ret = -ENOMEM;
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goto cleanup;
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}
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rawdev->dev_private = mz->addr;
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rawdev->dev_ops = ops;
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rawdev->device = dev;
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rawdev->driver_name = IOAT_PMD_RAWDEV_NAME_STR;
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idxd = rawdev->dev_private;
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*idxd = *base_idxd; /* copy over the main fields already passed in */
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idxd->rawdev = rawdev;
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idxd->mz = mz;
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return 0;
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cleanup:
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if (rawdev)
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rte_rawdev_pmd_release(rawdev);
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return ret;
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}
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@ -14,6 +14,10 @@
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* @b EXPERIMENTAL: these structures and APIs may change without prior notice
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*/
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#include <rte_spinlock.h>
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#include <rte_rawdev_pmd.h>
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#include "rte_ioat_rawdev.h"
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extern int ioat_pmd_logtype;
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#define IOAT_PMD_LOG(level, fmt, args...) rte_log(RTE_LOG_ ## level, \
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@ -24,4 +28,33 @@ extern int ioat_pmd_logtype;
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#define IOAT_PMD_ERR(fmt, args...) IOAT_PMD_LOG(ERR, fmt, ## args)
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#define IOAT_PMD_WARN(fmt, args...) IOAT_PMD_LOG(WARNING, fmt, ## args)
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struct idxd_pci_common {
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rte_spinlock_t lk;
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volatile struct rte_idxd_bar0 *regs;
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volatile struct rte_idxd_wqcfg *wq_regs;
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volatile struct rte_idxd_grpcfg *grp_regs;
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volatile void *portals;
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};
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struct idxd_rawdev {
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struct rte_idxd_rawdev public; /* the public members, must be first */
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struct rte_rawdev *rawdev;
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const struct rte_memzone *mz;
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uint8_t qid;
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uint16_t max_batches;
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union {
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struct idxd_pci_common *pci;
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} u;
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};
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extern int idxd_rawdev_create(const char *name, struct rte_device *dev,
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const struct idxd_rawdev *idxd,
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const struct rte_rawdev_ops *ops);
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extern int idxd_rawdev_close(struct rte_rawdev *dev);
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extern int idxd_rawdev_test(uint16_t dev_id);
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#endif /* _IOAT_PRIVATE_H_ */
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@ -7,6 +7,7 @@
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#include <rte_mbuf.h>
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#include "rte_rawdev.h"
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#include "rte_ioat_rawdev.h"
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#include "ioat_private.h"
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#define MAX_SUPPORTED_RAWDEVS 64
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#define TEST_SKIPPED 77
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@ -267,3 +268,9 @@ ioat_rawdev_test(uint16_t dev_id)
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free(ids);
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return -1;
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}
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int
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idxd_rawdev_test(uint16_t dev_id __rte_unused)
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{
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return 0;
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}
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@ -268,6 +268,70 @@ union rte_ioat_hw_desc {
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struct rte_ioat_pq_update_hw_desc pq_update;
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};
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/*** Definitions for Intel(R) Data Streaming Accelerator Follow ***/
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#define IDXD_CMD_SHIFT 20
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enum rte_idxd_cmds {
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idxd_enable_dev = 1,
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idxd_disable_dev,
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idxd_drain_all,
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idxd_abort_all,
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idxd_reset_device,
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idxd_enable_wq,
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idxd_disable_wq,
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idxd_drain_wq,
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idxd_abort_wq,
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idxd_reset_wq,
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};
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/* General bar0 registers */
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struct rte_idxd_bar0 {
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uint32_t __rte_cache_aligned version; /* offset 0x00 */
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uint64_t __rte_aligned(0x10) gencap; /* offset 0x10 */
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uint64_t __rte_aligned(0x10) wqcap; /* offset 0x20 */
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uint64_t __rte_aligned(0x10) grpcap; /* offset 0x30 */
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uint64_t __rte_aligned(0x08) engcap; /* offset 0x38 */
|
||||
uint64_t __rte_aligned(0x10) opcap; /* offset 0x40 */
|
||||
uint64_t __rte_aligned(0x20) offsets[2]; /* offset 0x60 */
|
||||
uint32_t __rte_aligned(0x20) gencfg; /* offset 0x80 */
|
||||
uint32_t __rte_aligned(0x08) genctrl; /* offset 0x88 */
|
||||
uint32_t __rte_aligned(0x10) gensts; /* offset 0x90 */
|
||||
uint32_t __rte_aligned(0x08) intcause; /* offset 0x98 */
|
||||
uint32_t __rte_aligned(0x10) cmd; /* offset 0xA0 */
|
||||
uint32_t __rte_aligned(0x08) cmdstatus; /* offset 0xA8 */
|
||||
uint64_t __rte_aligned(0x20) swerror[4]; /* offset 0xC0 */
|
||||
};
|
||||
|
||||
struct rte_idxd_wqcfg {
|
||||
uint32_t wqcfg[8] __rte_aligned(32); /* 32-byte register */
|
||||
};
|
||||
|
||||
#define WQ_SIZE_IDX 0 /* size is in first 32-bit value */
|
||||
#define WQ_THRESHOLD_IDX 1 /* WQ threshold second 32-bits */
|
||||
#define WQ_MODE_IDX 2 /* WQ mode and other flags */
|
||||
#define WQ_SIZES_IDX 3 /* WQ transfer and batch sizes */
|
||||
#define WQ_OCC_INT_IDX 4 /* WQ occupancy interrupt handle */
|
||||
#define WQ_OCC_LIMIT_IDX 5 /* WQ occupancy limit */
|
||||
#define WQ_STATE_IDX 6 /* WQ state and occupancy state */
|
||||
|
||||
#define WQ_MODE_SHARED 0
|
||||
#define WQ_MODE_DEDICATED 1
|
||||
#define WQ_PRIORITY_SHIFT 4
|
||||
#define WQ_BATCH_SZ_SHIFT 5
|
||||
#define WQ_STATE_SHIFT 30
|
||||
#define WQ_STATE_MASK 0x3
|
||||
|
||||
struct rte_idxd_grpcfg {
|
||||
uint64_t grpwqcfg[4] __rte_cache_aligned; /* 64-byte register set */
|
||||
uint64_t grpengcfg; /* offset 32 */
|
||||
uint32_t grpflags; /* offset 40 */
|
||||
};
|
||||
|
||||
#define GENSTS_DEV_STATE_MASK 0x03
|
||||
#define CMDSTATUS_ACTIVE_SHIFT 31
|
||||
#define CMDSTATUS_ACTIVE_MASK (1 << 31)
|
||||
#define CMDSTATUS_ERR_MASK 0xFF
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
@ -6,6 +6,7 @@ reason = 'only supported on x86'
|
||||
sources = files(
|
||||
'idxd_pci.c',
|
||||
'idxd_vdev.c',
|
||||
'ioat_common.c',
|
||||
'ioat_rawdev.c',
|
||||
'ioat_rawdev_test.c')
|
||||
deps += ['bus_pci',
|
||||
|
||||
@ -41,9 +41,20 @@ struct rte_ioat_generic_hw_desc {
|
||||
|
||||
/**
|
||||
* @internal
|
||||
* Structure representing a device instance
|
||||
* Identify the data path to use.
|
||||
* Must be first field of rte_ioat_rawdev and rte_idxd_rawdev structs
|
||||
*/
|
||||
enum rte_ioat_dev_type {
|
||||
RTE_IOAT_DEV,
|
||||
RTE_IDXD_DEV,
|
||||
};
|
||||
|
||||
/**
|
||||
* @internal
|
||||
* Structure representing an IOAT device instance
|
||||
*/
|
||||
struct rte_ioat_rawdev {
|
||||
enum rte_ioat_dev_type type;
|
||||
struct rte_rawdev *rawdev;
|
||||
const struct rte_memzone *mz;
|
||||
const struct rte_memzone *desc_mz;
|
||||
@ -79,6 +90,28 @@ struct rte_ioat_rawdev {
|
||||
#define RTE_IOAT_CHANSTS_HALTED 0x3
|
||||
#define RTE_IOAT_CHANSTS_ARMED 0x4
|
||||
|
||||
/**
|
||||
* @internal
|
||||
* Structure representing an IDXD device instance
|
||||
*/
|
||||
struct rte_idxd_rawdev {
|
||||
enum rte_ioat_dev_type type;
|
||||
void *portal; /* address to write the batch descriptor */
|
||||
|
||||
/* counters to track the batches and the individual op handles */
|
||||
uint16_t batch_ring_sz; /* size of batch ring */
|
||||
uint16_t hdl_ring_sz; /* size of the user hdl ring */
|
||||
|
||||
uint16_t next_batch; /* where we write descriptor ops */
|
||||
uint16_t next_completed; /* batch where we read completions */
|
||||
uint16_t next_ret_hdl; /* the next user hdl to return */
|
||||
uint16_t last_completed_hdl; /* the last user hdl that has completed */
|
||||
uint16_t next_free_hdl; /* where the handle for next op will go */
|
||||
|
||||
struct rte_idxd_user_hdl *hdl_ring;
|
||||
struct rte_idxd_desc_batch *batch_ring;
|
||||
};
|
||||
|
||||
/*
|
||||
* Enqueue a copy operation onto the ioat device
|
||||
*/
|
||||
|
||||
Loading…
Reference in New Issue
Block a user