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common/mlx5: fix relaxed ordering count object

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In order to improve performance relaxed ordering was enabled
when creating count object using Devx.

Currently rte enables this optimization by default when using
Devx.

This causes an issue when using firmware that does not have this
capability causing a count object failure.

In order to fix this issue a check of firmware capabilities was
added before enabling relaxed ordering.

Fixes: 53ac93f71a ("net/mlx5: create relaxed ordering memory regions")

Signed-off-by: Shiri Kuzin <shirik@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
This commit is contained in:
Shiri Kuzin 2020-05-12 15:21:45 +03:00 committed by Ferruh Yigit
parent 2b152cc97c
commit ffd5b302ba
4 changed files with 13 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/common/mlx5/mlx5_devx_cmds.c
View File

@ -451,6 +451,10 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,
attr->log_max_hairpin_num_packets = MLX5_GET
(cmd_hca_cap, hcattr, log_min_hairpin_wq_data_sz);
attr->vhca_id = MLX5_GET(cmd_hca_cap, hcattr, vhca_id);
attr->relaxed_ordering_write = MLX5_GET(cmd_hca_cap, hcattr,
relaxed_ordering_write);
attr->relaxed_ordering_read = MLX5_GET(cmd_hca_cap, hcattr,
relaxed_ordering_read);
attr->eth_net_offloads = MLX5_GET(cmd_hca_cap, hcattr,
eth_net_offloads);
attr->eth_virt = MLX5_GET(cmd_hca_cap, hcattr, eth_virt);

2
drivers/common/mlx5/mlx5_devx_cmds.h
View File

@ -100,6 +100,8 @@ struct mlx5_hca_attr {
uint32_t log_max_hairpin_wq_data_sz:5;
uint32_t log_max_hairpin_num_packets:5;
uint32_t vhca_id:16;
uint32_t relaxed_ordering_write:1;
uint32_t relaxed_ordering_read:1;
struct mlx5_hca_qos_attr qos;
struct mlx5_hca_vdpa_attr vdpa;
};

3
drivers/common/mlx5/mlx5_prm.h
View File

@ -1001,7 +1001,8 @@ struct mlx5_ifc_cmd_hca_cap_bits {
u8 reserved_at_d0[0xb];
u8 log_max_cq[0x5];
u8 log_max_eq_sz[0x8];
u8 reserved_at_e8[0x2];
u8 relaxed_ordering_write[0x1];
u8 relaxed_ordering_read[0x1];
u8 log_max_mkey[0x6];
u8 reserved_at_f0[0x8];
u8 dump_fill_mkey[0x1];

8
drivers/net/mlx5/mlx5_flow_dv.c
View File

@ -4100,8 +4100,8 @@ flow_dv_find_pool_by_id(struct mlx5_pools_container *cont, int id)
static struct mlx5_counter_stats_mem_mng *
flow_dv_create_counter_stat_mem_mng(struct rte_eth_dev *dev, int raws_n)
{
struct mlx5_ibv_shared *sh = ((struct mlx5_priv *)
(dev->data->dev_private))->sh;
struct mlx5_priv *priv = dev->data->dev_private;
struct mlx5_ibv_shared *sh = priv->sh;
struct mlx5_devx_mkey_attr mkey_attr;
struct mlx5_counter_stats_mem_mng *mem_mng;
volatile struct flow_counter_stats *raw_data;
@ -4133,7 +4133,9 @@ flow_dv_create_counter_stat_mem_mng(struct rte_eth_dev *dev, int raws_n)
mkey_attr.pg_access = 0;
mkey_attr.klm_array = NULL;
mkey_attr.klm_num = 0;
mkey_attr.relaxed_ordering = 1;
if (priv->config.hca_attr.relaxed_ordering_write &&
priv->config.hca_attr.relaxed_ordering_read)
mkey_attr.relaxed_ordering = 1;
mem_mng->dm = mlx5_devx_cmd_mkey_create(sh->ctx, &mkey_attr);
if (!mem_mng->dm) {
mlx5_glue->devx_umem_dereg(mem_mng->umem);