This patch adds new test case in which max. size of
chain mbufs has been used to compress random data dynamically.
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
Acked-by: Tomasz Cel <tomaszx.cel@intel.com>
Opendir() returns allocated storage which must be freed at the
end of function or in case any return on error. so freeing the
allocation using closedir in an error case.
Coverity issue: 323507
Coverity issue: 325880
Fixes: e7a45f3cc245 ("crypto/caam_jr: add UIO specific operations")
Cc: stable@dpdk.org
Signed-off-by: Gagandeep Singh <g.singh@nxp.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
CAAM return wrong digest value in AUTH only sg test case
because digest calculated on wrong length of data
Fixes: 71dd6b9d44e7 ("crypto/caam_jr: add scatter gather")
Cc: stable@dpdk.org
Signed-off-by: Gagandeep Singh <g.singh@nxp.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
build a shared descriptor accordingly if core and
CAAM endianness is same or different
Fixes: 6ef6beca8844 ("crypto/caam_jr: add enqueue/dequeue operations")
Cc: stable@dpdk.org
Signed-off-by: Gagandeep Singh <g.singh@nxp.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
IPSec Multi-buffer library has recently added API
that sets pointers depending on the architecture, at initiliazation,
in version 0.52.
AESNI MB PMD was updated with these changes, but not
the AESNI GCM PMD, which also uses the same library.
This makes the PMD to be only compatible with version 0.52,
but makes both PMD consistent on version compatibility,
plus adds support for AVX512.
Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
The supported algorithm tables for AESNI MB PMD were
missing some supported algorithms.
Fixes: 0e9f8507afcb ("crypto/aesni_mb: support AES-GCM algorithm")
Fixes: e5eecd3dc838 ("crypto/aesni_mb: support AES-GMAC")
Fixes: 11fdbf1b7866 ("crypto/aesni_mb: support plain SHA")
Cc: stable@dpdk.org
Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>
added check to see if a session for a device
has been initialised if it has return 0.
Fixes: 5d6c73dd5938 ("cryptodev: add reference count to session private data")
Cc: stable@dpdk.org
Signed-off-by: Marko Kovacevic <marko.kovacevic@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>
As a result of the cmac test running the test where
PT len is 65536 it should give a result back to the
user USER1: Error -1: Prepare op USER1: PT len 65536
as this MSG len is not supported. Issue was
that the application was not freeing the op properly after
a while causing the app to fail.
CRYPTODEV: rte_cryptodev_sym_session_create() line 1340:
couldn't get object from session mempool
USER1: Error -12: test block
USER1: Error -12: Failed test CMAC/req/CMAC.req
Fixes: cd255ccf5764 ("examples/fips_validation: support AES parsing")
Cc: stable@dpdk.org
Signed-off-by: Marko Kovacevic <marko.kovacevic@intel.com>
Application was failing as the HMAC and
Plain SHA fips request files are similar in a
way that they both have SHA- in the top section to
determine the hash algo and hash sizes. And HMAC having the
algo in the second line but the Plain SHA in the third
meant that when the HMAC files was used once it parsed the third
line Plain SHA was set as the algo and not HMAC.
USER1: Failed to get capability for cdev 0
USER1: Error -22: test block
[L=20 SHAAlg=SHA_2]
USER1: Error -22: Failed test /root/FIPS/HMAC/req/HMAC.req
Fixes: f4797bae0050 ("examples/fips_validation: support plain SHA")
Signed-off-by: Marko Kovacevic <marko.kovacevic@intel.com>
Mellanox BlueField is armv8 CPU having cortex-a72. The implementor ID is
0x41 (arm) and the primary part number is 0xd08 (cortex-a72).
Signed-off-by: Yongseok Koh <yskoh@mellanox.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Current default cache line size for armv8 CPUs having Implementor ID of
0x41 is 128 bytes, changing it to 64 bytes. Also, the max number of lcores
is changed to 16 from 256.
Signed-off-by: Yongseok Koh <yskoh@mellanox.com>
Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
If MLNX_OFED is installed, there's no .pc file installed for libraries and
dependency() can't find libraries by pkg-config. By adding fallback of
using cc.find_library(), libraries are properly located.
Fixes: e30b4e566f47 ("build: improve dependency handling")
Cc: stable@dpdk.org
Signed-off-by: Yongseok Koh <yskoh@mellanox.com>
Acked-by: Luca Boccassi <bluca@debian.org>
Disable octeontx for gcc 4.8.5 as compiler is emitting "internal compiler
error" for aarch64
Fixes: bd77f2d64c44 ("event/octeontx: build with meson")
Fixes: 4f760550a093 ("mk: disable OcteonTx for buggy compilers")
Fixes: f3af3e44a444 ("mk: disable OcteonTx for buggy compilers only on arm64")
Cc: stable@dpdk.org
Signed-off-by: Yongseok Koh <yskoh@mellanox.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Document the new value, as it's useful for distributions and users
who need to use a stable baseline -march
Signed-off-by: Luca Boccassi <bluca@debian.org>
Reviewed-by: Christian Ehrhardt <christian.ehrhardt@canonical.com>
Reviewed-by: Jerin Jacob <jerinj@marvell.com>
When building for generic distribution we need a stable baseline
architecture, or depending on the build worker the result will vary.
Force the default flags if the user explicitly sets machine=default
at configuration time.
Fixes: b1d48c41189a ("build: support ARM with meson")
Cc: stable@dpdk.org
Signed-off-by: Luca Boccassi <bluca@debian.org>
Acked-by: Bruce Richardson <bruce.richardson@intel.com>
Acked-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Add a function to the timer API that allows a caller to traverse a
specified set of timer lists, stopping each timer in each list,
and invoking a callback function.
Signed-off-by: Erik Gabriel Carrillo <erik.g.carrillo@intel.com>
Currently, the timer library uses a per-process table of structures to
manage skiplists of timers presumably because timers contain arbitrary
function pointers whose value may not resolve properly in other
processes.
However, if the same callback is used handle all timers, and that
callback is only invoked in one process, then it woud be safe to allow
the data structures to be allocated in shared memory, and to allow
secondary processes to modify the timer lists. This would let timers be
used in more multi-process scenarios.
The library's global variables are wrapped with a struct, and an array
of these structures is created in shared memory. The original APIs
are updated to reference the zeroth entry in the array. This maintains
the original behavior for both primary and secondary processes since
the set intersection of their coremasks should be empty [1]. New APIs
are introduced to enable the allocation/deallocation of other entries
in the array.
New variants of the APIs used to start and stop timers are introduced;
they allow a caller to specify which array entry should be used to
locate the timer list to insert into or delete from.
Finally, a new variant of rte_timer_manage() is introduced, which
allows a caller to specify which array entry should be used to locate
the timer lists to process; it can also process multiple timer lists per
invocation.
[1] https://doc.dpdk.org/guides/prog_guide/multi_proc_support.html#multi-process-limitations
Signed-off-by: Erik Gabriel Carrillo <erik.g.carrillo@intel.com>
These APIs are available in DPDK for last 4 releases
and used by multiple drivers.
Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
Acked-by: Stephen Hemminger <stephen@networkplumber.org>
Acked-by: Gaetan Rivet <gaetan.rivet@6wind.com>
The definition of CPU_AND differs from Linux to BSD, so we need to use
RTE_CPU_AND instead.
Fixes: f6baccbc2b3b ("examples/l2fwd-cat: add sample application for PQoS CAT and CDP")
Cc: stable@dpdk.org
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
Reviewed-by: David Marchand <david.marchand@redhat.com>
Acked-by: Luca Boccassi <bluca@debian.org>
The power library is not built on non-Linux systems, so skip the
distributor sample if it's not found, as it's a mandatory dependency.
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
Reviewed-by: David Marchand <david.marchand@redhat.com>
Acked-by: David Hunt <david.hunt@intel.com>
Acked-by: Luca Boccassi <bluca@debian.org>
Define variables for "is_linux", "is_freebsd" and "is_windows"
to make the code shorter for comparisons and more readable.
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
Reviewed-by: David Marchand <david.marchand@redhat.com>
Acked-by: Luca Boccassi <bluca@debian.org>
Within EAL we had a series of if statements for selecting the EAL directory
to use. Now that the directory names match those of the OS's they are for
we can instead just use a generated subdirectory name, shortening the code.
To avoid strange errors, we still need to check for unsupported OS's, but
do this check up-front in the config meson.build file.
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
Reviewed-by: David Marchand <david.marchand@redhat.com>
Acked-by: Luca Boccassi <bluca@debian.org>
The use of "==" is non-standard extension from bash, so use "="
for comparisons instead.
Cc: stable@dpdk.org
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
Acked-by: Luca Boccassi <bluca@debian.org>
Older versions of GCC, such as on Redhat/CentOS 7, don't support
-march=nehalem, but need -march=corei7 instead.
Cc: stable@dpdk.org
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
Acked-by: Luca Boccassi <bluca@debian.org>
If either gcc or clang are missing, skip doing those builds.
This allows a setup to only do, e.g. gcc tests.
Cc: stable@dpdk.org
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
Acked-by: Luca Boccassi <bluca@debian.org>
Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
The arguments being passed will cause failures on laptops that have,
for instance, 2 cores only. Most of the tests don't require more
than a single core. Some require multiple cores (but those tests
should be modified to 'SKIP' when the correct number of cores
aren't available).
The unit test results shouldn't be impacted by this change, but it
allows for a future enhancement to pass flags such as '--no-huge'.
Also include a fix to a reported issue with running on FreeBSD.
Signed-off-by: Aaron Conole <aconole@redhat.com>
Reviewed-by: David Marchand <david.marchand@redhat.com>
Acked-by: Luca Boccassi <bluca@debian.org>
Acked-by: Bruce Richardson <bruce.richardson@intel.com>
This helps in two ways:
1. When looking at travis page for dpdk, it's a visual distinction
2. For ccache support, the build IDs include the 'env', so we get unique
cache data.
Signed-off-by: Aaron Conole <aconole@redhat.com>
Reviewed-by: David Marchand <david.marchand@redhat.com>
Acked-by: Luca Boccassi <bluca@debian.org>
We try to make the planet happy travis builds dpdk.
Also, the 'sudo' flag was recently deprecated. Drop it.
Suggested-by: Luca Boccassi <bluca@debian.org>
Signed-off-by: Aaron Conole <aconole@redhat.com>
Reviewed-by: David Marchand <david.marchand@redhat.com>
Acked-by: Luca Boccassi <bluca@debian.org>
Currently, when symbols get promoted from the EXPERIMENTAL section to a
stable ABI section, the script complains they should go to the
EXPERIMENTAL section.
Example:
ERROR: symbol rte_devargs_add is added in the DPDK_19.05 section, but is
expected to be added in the EXPERIMENTAL section of the version map
This is legit.
Moving from a stable ABI to another is also allowed, but must have gone
through the proper process.
Fixes: 4bec48184e33 ("devtools: add checks for ABI symbol addition")
Cc: stable@dpdk.org
Signed-off-by: David Marchand <david.marchand@redhat.com>
Acked-by: Neil Horman <nhorman@tuxdriver.com>
Currently, RTE_* flags are set based on the implementer ID but there might
be some micro arch specific differences from the same vendor
eg. CACHE_LINESIZE. Add support to set micro arch specific flags.
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Introduce rte_cc_has_argument() Makefile helper to
check a given argument is support by the compiler.
Example Usage:
include $(RTE_SDK)/mk/rte.helper.mk
MACHINE_CFLAGS += $(call rte_cc_has_argument, -mcpu=octeontx2)
This would allow adding -mcpu=octeontx2 in MACHINE_CFLAGS
if it is only supported by the compiler. The use case for such
scheme is to enable the mcpu optimization if the compiler
supports else it needs to compile the source code without
any errors.
This patch also moves inclusion of toolchain's rte.vars.mk
to before the machine's rte.vars.mk inclusion to make
correct CC available for the cross compile case.
Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Add ticketlock_autotest implementation in python.
Fixes: efbcdaa55b93 ("test/ticketlock: add test cases")
Signed-off-by: Joyce Kong <joyce.kong@arm.com>
Reviewed-by: Phil Yang <phil.yang@arm.com>
Tested-by: Phil Yang <phil.yang@arm.com>
Commit 267d32de46a8 ("net/qede: support generic flow API")
added a support for RTE_FLOW APIs but did not update the feature
support matrix.
Fixes: 267d32de46a8 ("net/qede: support generic flow API")
Cc: stable@dpdk.org
Signed-off-by: Shahed Shaikh <shshaikh@marvell.com>
This patch stopped LLDP by default to avoid the statistics error.
Signed-off-by: Qiming Yang <qiming.yang@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
No need to add additional vlan tag size for max packet size, since
for i40e, the queue's Rx Max Frame Size (rxq->max_pkt_len) already
includes the vlan header size.
Fixes: a3c83a2527e1 ("net/i40e: enable runtime queue setup")
Fixes: 4861cde46116 ("i40e: new poll mode driver")
Fixes: c1715402df8f ("i40evf: fix jumbo frame support")
Cc: stable@dpdk.org
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
The result of the endian conversion was not being used incorrectly.
Fixes: b11cceb83a34 ("net/bnxt: support timesync")
Cc: stable@dpdk.org
Reported-by: Thomas Monjalon <thomas@monjalon.net>
Signed-off-by: Somnath Kotur <somnath.kotur@broadcom.com>
The vlan pattern handler currently assumes the NIC always strips vlan
header from the L2 buffer, regardless of the vlan strip setting. But,
with older VIC models, the vlan header is actually present in the L2
buffer if stripping is disabled. So in this case, the inner ether type
needs to be shifted by that much.
Fixes: 6ced137607d0 ("net/enic: flow API for NICs with advanced filters enabled")
Cc: stable@dpdk.org
Signed-off-by: Hyong Youb Kim <hyonkim@cisco.com>
Reviewed-by: John Daley <johndale@cisco.com>
There is need for users to set configuration of HEX number for RSS
key. The key byte should be pass down as hex number not as char
string. This patch enable cmdline flow parse HEX number,
in order to not using string which pass ASIC number.
Fixes: f4d623f96119 ("app/testpmd: fix missing RSS fields in flow action")
Cc: stable@dpdk.org
Signed-off-by: Wei Zhao <wei.zhao1@intel.com>
Tested-by: Yuan Peng <yuan.peng@intel.com>
Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
Currently, the raw item is always preceded by a UDP header, and both
land in the L4 pattern buffer. So consider the UDP header size when
checking if the raw spec fits in the L4 buffer.
Coverity issue: 336796, 336850
Fixes: 477959e6eeb0 ("net/enic: enable limited support for raw flow item")
Signed-off-by: Hyong Youb Kim <hyonkim@cisco.com>
Reviewed-by: John Daley <johndale@cisco.com>
UAR (User Access Region) register does not need to be remapped for
primary process but it should be remapped only for secondary process.
UAR register table is in the process private structure in
rte_eth_devices[],
(struct mlx4_proc_priv *)rte_eth_devices[port_id].process_private
The actual UAR table follows the data structure and the table is used
for both Tx and Rx.
For Tx, BlueFlame in UAR is used to ring the doorbell.
MLX4_TX_BFREG(txq) is defined to get a register for the txq. Processes
access its own private data to acquire the register from the UAR table.
For Rx, the doorbell in UAR is required in arming CQ event. However, it
is a known issue that the register isn't remapped for secondary process.
Signed-off-by: Yongseok Koh <yskoh@mellanox.com>
Acked-by: Shahaf Shuler <shahafs@mellanox.com>
UAR (User Access Region) register does not need to be remapped for
primary process but it should be remapped only for secondary process.
UAR register table is in the process private structure in
rte_eth_devices[],
(struct mlx5_proc_priv *)rte_eth_devices[port_id].process_private
The actual UAR table follows the data structure and the table is used
for both Tx and Rx.
For Tx, BlueFlame in UAR is used to ring the doorbell.
MLX5_TX_BFREG(txq) is defined to get a register for the txq. Processes
access its own private data to acquire the register from the UAR table.
For Rx, the doorbell in UAR is required in arming CQ event. However, it
is a known issue that the register isn't remapped for secondary process.
Signed-off-by: Yongseok Koh <yskoh@mellanox.com>
Queue index is redundantly stored for both Rx and Tx structures.
E.g. txq_ctrl->idx and txq->stats.idx. Both are consolidated to single
storage - rxq->idx and txq->idx.
Also, rxq and txq are moved to the beginning of its control structure
(rxq_ctrl and txq_ctrl) for cacheline alignment.
Signed-off-by: Yongseok Koh <yskoh@mellanox.com>
Acked-by: Shahaf Shuler <shahafs@mellanox.com>
