Commit Graph

1305 Commits

Author SHA1 Message Date
David Marchand
b1a3e0f773 eal/bsd: fix core detection
Following "options parsing" patchset (commit d7cb626f and 489a9d6c), core
detection is not working correctly on bsd.

./x86_64-native-bsdapp-gcc/app/test -c f -n 4 -- -i
[...]
EAL: lcore 0 unavailable
EAL: invalid coremask

Align bsd to linux:
- commit f563a372 "eal: fix recording of detected/enabled logical cores"
- commit 4f04db8b "eal: check coremask against detected lcores"

Reported-by: Zhan, Zhaochen <zhaochen.zhan@intel.com>
Signed-off-by: David Marchand <david.marchand@6wind.com>
Acked-by: Bruce Richardson <bruce.richardson@intel.com>
Acked-by: Neil Horman <nhorman@tuxdriver.com>
Tested-by: Zhaochen Zhan <zhaochen.zhan@intel.com>
2014-10-09 17:52:06 +02:00
Bruce Richardson
17c696b4ff mbuf: comment for ctrl mbuf flag
Add in a doxygen comment for the ctrl mbuf flag definition.

Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
Acked-by: Thomas Monjalon <thomas.monjalon@6wind.com>
2014-10-08 14:45:36 +02:00
Bruce Richardson
578cca42da mbuf: update Rx flag format
Update the format of the RX flags to match that of the TX flags. In
general the flags are now specified as "1ULL << X", with a few
exceptions.

Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
Acked-by: Thomas Monjalon <thomas.monjalon@6wind.com>
2014-10-08 14:45:14 +02:00
Bruce Richardson
dff38e8e0d mbuf: group Tx flags near end of field
This patch takes the existing TX flags defined for the mbuf and shifts
each uniquely defined one left so that additional RX flags can be
defined without having RX and TX flags mixed together. Under the new
scheme, RX flags start at bit 0 and work left, TX flags start at bit 55
and work right, and bits 56-63 are reserved for generic mbuf use, not
for offloads.

Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
Reviewed-by: Neil Horman <nhorman@tuxdriver.com>
Acked-by: Thomas Monjalon <thomas.monjalon@6wind.com>
2014-10-08 14:43:47 +02:00
Bruce Richardson
fa73fe80a7 app/testpmd: change rxfreet default to 32
To improve performance by using bulk alloc or vectored RX routines, we
need to set rx free threshold (rxfreet) value to 32, so make this the
testpmd default.

Thirty-two is the minimum setting needed to enable either the
bulk alloc or vector RX routines inside the ixgbe driver, so it's
best made the default for that reason. Please see
"check_rx_burst_bulk_alloc_preconditions()" in ixgbe_rxtx.c, and
RX function assignment logic in "ixgbe_dev_rx_queue_setup()" in
the same file.

The difference in IO performance for testpmd when called without any
optional parameters, and using 10G NICs using the ixgbe driver, can be
significant - approx 25% or more.

Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
Acked-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
2014-10-08 14:24:59 +02:00
Bruce Richardson
d803387a7f ixgbe: add prefetch to improve slow-path tx perf
Make a small improvement to slow path TX performance by adding in a
prefetch for the second mbuf cache line.
Also move assignment of l2/l3 length values only when needed.

What I've done with the prefetches is two-fold:
1) changed it from prefetching the mbuf (first cache line) to prefetching
the mbuf pool pointer (second cache line) so that when we go to access
the pool pointer to free transmitted mbufs we don't get a cache miss. When
clearing the ring and freeing mbufs, the pool pointer is the only mbuf
field used, so we don't need that first cache line.
2) changed the code to prefetch earlier - in effect to prefetch one mbuf
ahead. The original code prefetched the mbuf to be freed as soon as it
started processing the mbuf to replace it. Instead now, every time we
calculate what the next mbuf position is going to be we prefetch the mbuf
in that position (i.e. the mbuf pool pointer we are going to free the mbuf
to), even while we are still updating the previous mbuf slot on the ring.
This gives the prefetch much more time to resolve and get the data we need
in the cache before we need it.

In terms of performance difference, a quick sanity test using testpmd
on a Xeon (Sandy Bridge uarch) platform showed performance increases
between approx 8-18%, depending on the particular RX path used in
conjuntion with this TX path code.

Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
Acked-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
2014-10-08 14:24:59 +02:00
Bruce Richardson
a62bfb72b9 mbuf: switch vlan_tci and reserved2 fields
Move the vlan_tci field up by two bytes in the mbuf data structure. This
has two effects:
* Ensures the the ixgbe vector driver places the vlan tag in the correct
  place in the mbuf.
* Allows a second vlan tag field, if one is added in the future, to be
  placed after the existing vlan field, rather than before.

Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
Acked-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
2014-10-08 14:24:59 +02:00
Bruce Richardson
4cd917b308 mbuf: add userdata pointer field
While some applications may store metadata about packets in the packet
mbuf headroom, this is not a workable solution for packet metadata which
is either:
* larger than the headroom (or headroom is needed for adding pkt headers)
* needs to be shared or copied among packets

To support these use cases in applications, we reserve a general
"userdata" pointer field inside the second cache-line of the mbuf. This
is better than having the application store the pointer to the external
metadata in the packet headroom, as it saves an additional cache-line
from being used.

Apart from storing metadata, this field also provides a general 8-byte
scratch space inside the mbuf for any other application uses that are
applicable.

Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
Acked-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
2014-10-08 14:24:59 +02:00
Bruce Richardson
7f78e67701 mbuf: ensure next pointer is set to null on free
The receive functions for packets do not modify the next pointer so
the next pointer should always be cleared on mbuf free, just in case.
The slow-path TX needs to clear it, and the standard mbuf free function
also needs to clear it. Fast path TX does not handle chained mbufs so
is unaffected

Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
Acked-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
2014-10-08 14:12:31 +02:00
Helin Zhang
3043ce5011 i40e/base: fix arq_event_info struct
Overloading the 'msg_size' field in the 'arq_event_info' struct
is a bad idea. It leads to bugs when the structure is used in a
loop, since the input value (buffer size) is overwritten by the
output value (actual message length). The fix introduces one
more field of 'buf_len' for the buffer size, and renames the
field of 'msg_size' to 'msg_len' for the real message size.

Signed-off-by: Helin Zhang <helin.zhang@intel.com>
Reviewed-by: Chen Jing <jing.d.chen@intel.com>
Tested-by: HuilongX Xu <huilongx.xu@intel.com>
2014-10-07 18:02:11 +02:00
Helin Zhang
a00b77ed12 i40e/base: debug write register request
The firmware api request of writes to hardware registers should be
exposed to driver. The new API of 'i40e_aq_debug_write_register'
is introduced for that.

Signed-off-by: Helin Zhang <helin.zhang@intel.com>
Reviewed-by: Chen Jing <jing.d.chen@intel.com>
Tested-by: HuilongX Xu <huilongx.xu@intel.com>
2014-10-07 18:02:11 +02:00
Helin Zhang
011c9d28cd i40e/base: support 10G base T
10G base T type support is added.

Signed-off-by: Helin Zhang <helin.zhang@intel.com>
Reviewed-by: Chen Jing <jing.d.chen@intel.com>
Tested-by: HuilongX Xu <huilongx.xu@intel.com>
2014-10-07 18:02:11 +02:00
Helin Zhang
fba8023803 i40e/base: get link status to report flow control settings
The fix is to use get_link_status but not get_phy_capabilities
for reporting FC settings.

Signed-off-by: Helin Zhang <helin.zhang@intel.com>
Reviewed-by: Chen Jing <jing.d.chen@intel.com>
Tested-by: HuilongX Xu <huilongx.xu@intel.com>
2014-10-07 18:02:11 +02:00
Helin Zhang
93debffce8 i40e/base: workaround for firmware version
The workaround helps fix the API if the FW is 4.2 or later.
In addition, an unreachable 'break' statement has been removed.

Signed-off-by: Helin Zhang <helin.zhang@intel.com>
Reviewed-by: Chen Jing <jing.d.chen@intel.com>
Tested-by: HuilongX Xu <huilongx.xu@intel.com>
2014-10-07 18:02:11 +02:00
Helin Zhang
d0a51bf9f9 i40e/base: get rid of sparse warnings
There are variables that represent values in little endian.
Adding prefix of '__Le' can remove warnings during sparse
checks. In addition, remove some unreachable 'break' statements,
and add 'UL' on a couple of constants.

Signed-off-by: Helin Zhang <helin.zhang@intel.com>
Reviewed-by: Chen Jing <jing.d.chen@intel.com>
Tested-by: HuilongX Xu <huilongx.xu@intel.com>
2014-10-07 18:02:11 +02:00
Helin Zhang
2408e5b406 i40e/base: force a shifted bit to be unsigned
Force a shifted '1' to be 'unsigned' to avoid shifting a signed int.

Signed-off-by: Helin Zhang <helin.zhang@intel.com>
Reviewed-by: Chen Jing <jing.d.chen@intel.com>
Tested-by: HuilongX Xu <huilongx.xu@intel.com>
2014-10-07 18:02:11 +02:00
Helin Zhang
f5fb399ac5 i40e/base: remove code for TPH
The code wrapped in '#ifdef I40E_TPH_SUPPORT' was added
to check if 'TPH' (TLP Processing Hints) is supported, and enable it.
It is not used currently and can be removed.

Signed-off-by: Helin Zhang <helin.zhang@intel.com>
Reviewed-by: Chen Jing <jing.d.chen@intel.com>
Tested-by: HuilongX Xu <huilongx.xu@intel.com>
2014-10-07 18:02:11 +02:00
Helin Zhang
f739ac5e90 i40e/base: remove code for software validation only
The code wrapped in '#ifdef I40E_DCB_SW' is currently for software
validation only, it should be removed at all.

Signed-off-by: Helin Zhang <helin.zhang@intel.com>
Reviewed-by: Chen Jing <jing.d.chen@intel.com>
Tested-by: HuilongX Xu <huilongx.xu@intel.com>
2014-10-07 18:02:11 +02:00
Helin Zhang
ea1e178773 i40e/base: remove useless code for pre-boot
The code wrapped in '#ifdef PREBOOT_SUPPORT' was added for
queue context initialization specifically for A0 silicon.
As A0 silicon has gone for a long time, the code should be
removed at all. In addition, the checks of 'QV_RELEASE'
and 'PREBOOT_SUPPORT' are also not needed anymore and can
be removed.

Signed-off-by: Helin Zhang <helin.zhang@intel.com>
Reviewed-by: Chen Jing <jing.d.chen@intel.com>
Tested-by: HuilongX Xu <huilongx.xu@intel.com>
2014-10-07 18:02:10 +02:00
Helin Zhang
55d63d0251 i40e/base: remove useless code for Solaris
The code wrapped in '#ifdef DMA_SYNC_SUPPORT' was written specially
for Solaris, it is not needed anymore for others including DPDK.

Signed-off-by: Helin Zhang <helin.zhang@intel.com>
Reviewed-by: Chen Jing <jing.d.chen@intel.com>
Tested-by: HuilongX Xu <huilongx.xu@intel.com>
2014-10-07 18:02:10 +02:00
Helin Zhang
8340db53e5 i40e/base: remove test code for ethtool
The code wrapped in '#ifdef ETHTOOL_TEST' in i40e_diag.c is for
ethtool testing only, it is not needed anymore and can be removed.

Signed-off-by: Helin Zhang <helin.zhang@intel.com>
Reviewed-by: Chen Jing <jing.d.chen@intel.com>
Tested-by: HuilongX Xu <huilongx.xu@intel.com>
2014-10-07 18:02:10 +02:00
Helin Zhang
9435d9b1ec i40e/base: support nvmupdate by default
'nvmupdate' is intended to support the userland NVMUpdate tool for
Fortville eeprom. These code changes is to remove the conditional
compile macro, and support those by default. In addition, renaming
all 'errno' to avoid any compile warning or error.

Signed-off-by: Helin Zhang <helin.zhang@intel.com>
Reviewed-by: Chen Jing <jing.d.chen@intel.com>
Tested-by: HuilongX Xu <huilongx.xu@intel.com>
2014-10-07 17:38:24 +02:00
Helin Zhang
3170192e69 i40e/base: make the indentation more consistent
In share code, 'tab' is used to align values rather than 'space'.
The changes in i40e_adminq_cmd.h is to make the indentation more
consistent in share code.

Signed-off-by: Helin Zhang <helin.zhang@intel.com>
Reviewed-by: Chen Jing <jing.d.chen@intel.com>
Tested-by: HuilongX Xu <huilongx.xu@intel.com>
2014-10-07 17:35:53 +02:00
Ouyang Changchun
1b9ea09c06 ixgbe: support X550
Update device id and PF driver to support X550.

Signed-off-by: Changchun Ouyang <changchun.ouyang@intel.com>
2014-10-07 17:01:08 +02:00
Ouyang Changchun
d2e72774e5 ixgbe/base: support X550
Add new file to support controller X550, therefore update the Makefile
and README file. It also updates the API functions, DCB related functions,
mailbox related functions, etc to support X550.
In addition, some new macros used by X550 are added.

Signed-off-by: Changchun Ouyang <changchun.ouyang@intel.com>
[Thomas: merge dependent patches]
2014-10-07 17:00:52 +02:00
Ouyang Changchun
9fe892eb08 ixgbe/base: i2c combined read/write
Signed-off-by: Changchun Ouyang <changchun.ouyang@intel.com>
2014-10-07 17:00:52 +02:00
Ouyang Changchun
ea344b73c8 ixgbe/base: malicious driver detection
Signed-off-by: Changchun Ouyang <changchun.ouyang@intel.com>
[Thomas: split patch]
2014-10-07 17:00:52 +02:00
Ouyang Changchun
4beb35c664 ixgbe/base: iosf sideband read/write
Signed-off-by: Changchun Ouyang <changchun.ouyang@intel.com>
[Thomas: split patch]
2014-10-07 17:00:36 +02:00
Ouyang Changchun
835647548d ixgbe/base: anti spoofing
Signed-off-by: Changchun Ouyang <changchun.ouyang@intel.com>
[Thomas: split patch]
2014-10-07 16:51:59 +02:00
Ouyang Changchun
6c48ee06a9 ixgbe/base: source address pruning
Signed-off-by: Changchun Ouyang <changchun.ouyang@intel.com>
[Thomas: split patch]
2014-10-07 16:51:59 +02:00
Ouyang Changchun
efa2dc5b09 ixgbe/base: support EEE
Signed-off-by: Changchun Ouyang <changchun.ouyang@intel.com>
[Thomas: split patch]
2014-10-07 16:51:59 +02:00
Ouyang Changchun
f5b0a41961 ixgbe/base: dma coalescing
Signed-off-by: Changchun Ouyang <changchun.ouyang@intel.com>
[Thomas: split patch]
2014-10-07 16:51:59 +02:00
Ouyang Changchun
21c5ad42ea ixgbe/base: thermal sensor
Signed-off-by: Changchun Ouyang <changchun.ouyang@intel.com>
[Thomas: split patch]
2014-10-07 16:51:59 +02:00
Ouyang Changchun
e7dc3c78dd ixgbe/base: fdir cloud mode
Supports flow director cloud mode in IXGBE base code.

Signed-off-by: Changchun Ouyang <changchun.ouyang@intel.com>
2014-10-07 16:51:59 +02:00
Ouyang Changchun
d17d0b7a24 ixgbe/base: reset VF registers
Reset VF registers to initial values in IXGBE base code.

Signed-off-by: Changchun Ouyang <changchun.ouyang@intel.com>
2014-10-07 16:51:59 +02:00
Ouyang Changchun
558136b918 ixgbe/base: clean phy sfp handling
Remove 10GBASE_ER support.
Always support 1000BASE_LX.

Signed-off-by: Changchun Ouyang <changchun.ouyang@intel.com>
[Thomas: split patch]
2014-10-07 16:24:35 +02:00
Ouyang Changchun
b94a06c1b4 ixgbe/base: support qsfp and lco
- Implement functions to do I2C byte read and write
- Support 82599_QSFP_SF_QP and 82599_LS

Signed-off-by: Changchun Ouyang <changchun.ouyang@intel.com>
[Thomas: split patch]
2014-10-07 15:56:39 +02:00
Ouyang Changchun
4ef84d5a22 ixgbe/base: move phy sfp detection in a function
Signed-off-by: Changchun Ouyang <changchun.ouyang@intel.com>
[Thomas: split patch]
2014-10-07 15:56:15 +02:00
Ouyang Changchun
d66791389c ixgbe/base: rework semaphore
- Store lan_id and physical semaphore mask into hardware physical information,
and use them to control read and write physical registers in IXGBE base code.
- Extend mask from 16 bits to 32 bits for releasing or acquiring SWFW semaphore
in IXGBE base code. It is used in reading and writing I2C byte.

Signed-off-by: Changchun Ouyang <changchun.ouyang@intel.com>
[Thomas: merge dependent patches]
2014-10-07 15:43:27 +02:00
Ouyang Changchun
df0799e764 ixgbe/base: remove unnecessary delay
Remove unnecessary delay when setting up physical link and negotiating
in IXGBE base code.

Signed-off-by: Changchun Ouyang <changchun.ouyang@intel.com>
2014-10-07 15:43:27 +02:00
Ouyang Changchun
dc7508f1fa ixgbe/base: wait longer while polling X540 flash update
It need wait for 5 ms for polling EEC register in IXGBE X540 base code.

Signed-off-by: Changchun Ouyang <changchun.ouyang@intel.com>
2014-10-07 15:43:27 +02:00
Ouyang Changchun
6a236f9625 ixgbe/base: wait longer for VF link status
Signed-off-by: Changchun Ouyang <changchun.ouyang@intel.com>
[Thomas: split patch]
2014-10-07 15:43:27 +02:00
Ouyang Changchun
c2a4a29795 ixgbe/base: fix flow control comment
Signed-off-by: Changchun Ouyang <changchun.ouyang@intel.com>
[Thomas: split patch]
2014-10-07 15:43:27 +02:00
Ouyang Changchun
36f43e8679 ixgbe/base: refactor manageability block communication
Introduce a new argument to let caller determine if it need read and
return data or not after executing host interface command in IXGBE base code.

Signed-off-by: Changchun Ouyang <changchun.ouyang@intel.com>
2014-10-07 15:33:34 +02:00
Ouyang Changchun
fb42f38ee8 ixgbe/base: refactor eeprom checksum calculation
Refines function to let eeprom checksum calculation return
either a negative error code on error, or the 16-bit checksum
in IXGBE base code.

Signed-off-by: Changchun Ouyang <changchun.ouyang@intel.com>
2014-10-07 15:33:16 +02:00
Ouyang Changchun
c313c942fe ixgbe/base: factorize fdir command complete check
Implements a function to check command complete for flow director in
IXGBE base code, and replaces related code snippet with this function.

Signed-off-by: Changchun Ouyang <changchun.ouyang@intel.com>
2014-10-07 15:32:58 +02:00
Ouyang Changchun
c8fb5832be ixgbe/base: move manageability function
Manageability query is a common routine (not specific to 82599).

Signed-off-by: Changchun Ouyang <changchun.ouyang@intel.com>
[Thomas: split patch]
2014-10-07 15:14:03 +02:00
Ouyang Changchun
0b6683fa75 ixgbe/base: new error types
This patch defines new error type in IXGBE base code; they are
used to report different kinds of error.

Signed-off-by: Changchun Ouyang <changchun.ouyang@intel.com>
2014-10-07 15:14:03 +02:00
Ouyang Changchun
66ae737285 ixgbe/base: various clean up
Signed-off-by: Changchun Ouyang <changchun.ouyang@intel.com>
2014-10-03 14:45:24 +02:00
Ouyang Changchun
6fe00c9490 ixgbe/base: minor changes
Signed-off-by: Changchun Ouyang <changchun.ouyang@intel.com>
2014-10-03 14:45:23 +02:00