9 Commits

Author SHA1 Message Date
Ferruh Yigit
295968d174 ethdev: add namespace
Add 'RTE_ETH' namespace to all enums & macros in a backward compatible
way. The macros for backward compatibility can be removed in next LTS.
Also updated some struct names to have 'rte_eth' prefix.

All internal components switched to using new names.

Syntax fixed on lines that this patch touches.

Signed-off-by: Ferruh Yigit <ferruh.yigit@intel.com>
Acked-by: Tyler Retzlaff <roretzla@linux.microsoft.com>
Acked-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Acked-by: Wisam Jaddo <wisamm@nvidia.com>
Acked-by: Rosen Xu <rosen.xu@intel.com>
Acked-by: Chenbo Xia <chenbo.xia@intel.com>
Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>
Acked-by: Somnath Kotur <somnath.kotur@broadcom.com>
2021-10-22 18:15:38 +02:00
Vamsi Attunuru
29bb974576 net/octeontx2: fix flow control initial state
Currently when application requests for RTE_FC_NONE earlier
than PMD's internal fc mode update, flow control set routine
is returning without updating the flow control state.

Patch updates the PMD's internal fc mode details during
dev_configure to ensure any flow control set requests
issued later are handled properly.

Fixes: 609945f1ce90 ("net/octeontx2: support flow control")
Cc: stable@dpdk.org

Signed-off-by: Vamsi Attunuru <vattunuru@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
2020-02-15 10:23:07 +01:00
Kiran Kumar K
184a323573 net/octeontx2: fix Tx flow control for HIGIG
Tx flow controlled is disabled in the Ax silicon version due to an errata.
This errata is not applicable for HIGIG Tx flow control, therefore
not enabling in HIGIG case.

Fixes: 602009ee2dfb ("net/octeontx2: support HIGIG2")
Cc: stable@dpdk.org

Signed-off-by: Kiran Kumar K <kirankumark@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
2020-02-05 09:51:21 +01:00
Subrahmanyam Nilla
c261680cdb net/octeontx2: support SDP interface
System DPI Packet Interface Unit (SDP) is a co-processor
of OCTEON TX2 which provides PCIe endpoint support for a
remote host to DMA packets into and out of the OCTEON TX2 SoC.
SDP interface comes in to live only when it is connected in
EP mode. It exposes input and output queue pairs to remote host
for instruction input and packet output. It can be used as
a communication channel between remote host and OCTEON TX2.
Host machine needs to use corresponding user/kernel mode
driver to communicate with SDP interface on OCTEON TX2 SoC.

SDP interface support is limited to SDP PF device now.
No SDP VF support.

Signed-off-by: Subrahmanyam Nilla <snilla@marvell.com>
Signed-off-by: Venkateshwarlu Nalla <venkatn@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
2019-11-08 23:15:05 +01:00
Vamsi Attunuru
8f3afc1359 net/octeontx2: skip flow control on LBK ports
LBK interface does not support any flow control related
HW configurations.

Skip flow control set requests on LBK bound ethports.

Signed-off-by: Harman Kalra <hkalra@marvell.com>
Signed-off-by: Vamsi Attunuru <vattunuru@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
2019-11-08 23:15:04 +01:00
Nithin Dabilpuram
30c234e4e9 net/octeontx2: allow VFs to enable back pressure
Allow VFs to enable backpressure for performance reasons.
The backpressure control is with kernel AF driver that will enable
backpressure even if one PF/VF requests it and disable it only
after all the PFs/VFs request for disable.

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
2019-10-08 12:14:31 +02:00
Nithin Dabilpuram
8d0715f054 net/octeontx2: support 96xx A1 silicon revision
Update workaround changes for erratas that are fixed on 96xx A1.
This patch also enables cq drop for all the passes for
maintaining performance along with updating a default
Rx ring size in dev_info.

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
2019-08-05 18:36:25 +02:00
Nithin Dabilpuram
d1d823e7a8 common/octeontx2: support CNF95xx SoC
Update platform support of CNF95xx in documentation and
also, update the HW cap based on PCI subsystem id and revision id.
This patch also changes HW capability handling to be based on
PCI Revision ID. PCI Revision ID contains a unique identifier
to identify chip, major and minor revisions.

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
2019-07-14 15:39:49 +02:00
Vamsi Attunuru
609945f1ce net/octeontx2: support flow control
Add flow control operations and exposed
otx2_nix_update_flow_ctrl_mode() to enable on the
configured mode in dev_start().

Signed-off-by: Vamsi Attunuru <vattunuru@marvell.com>
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
2019-07-05 01:52:01 +02:00