12 Commits

Author SHA1 Message Date
Leyi Rong
dfbb0b98d4 net/ice/base: refactor zeroing bitmap size
A couple of places in the code use a 'sizeof(bitmap) * BITS_PER_BYTE'
construction to calculate the size of the bitmap when calling
ice_zero_bitmap. Instead of doing this, just use the same value as in
the ice_declare_bitmap declaration.

Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Leyi Rong <leyi.rong@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2019-06-28 20:31:49 +02:00
Leyi Rong
fdafeee39a net/ice/base: refactor VSI node scheduler
Refactored VSI node sched code to use port_info ptr as call arg.

The declaration of VSI node getter function has been modified to use
pointer to ice_port_info structure instead of pointer to hw structure.
This way suitable port_info structure is used to find VSI node.

Signed-off-by: Grzegorz Nitka <grzegorz.nitka@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Leyi Rong <leyi.rong@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2019-06-28 20:31:49 +02:00
Leyi Rong
42fde0faf9 net/ice/base: cleanup unused code
Cleanup the useless code.

Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Leyi Rong <leyi.rong@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2019-06-28 20:31:49 +02:00
Leyi Rong
e4b73bee79 net/ice/base: fix rate limit burst size calculation
When the MSB is not set, the lower 11 bits do not represent bytes, but
chunks of 64 bytes. Adjust the rate limit burst size calculation
accordingly, and update the comments to indicate the way the hardware
actually works.

Fixes: 93e84b1bfc92 ("net/ice/base: add basic Tx scheduler")
Cc: stable@dpdk.org

Signed-off-by: Ben Shelton <benjamin.h.shelton@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Leyi Rong <leyi.rong@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2019-06-28 20:31:48 +02:00
Leyi Rong
39e30e38c4 net/ice/base: add sibling head to parse nodes
There was a bug in the previous code which never traverses all the
children to get the first node of the requested layer.

Added a sibling head pointer to point the first node of each layer
per TC. This helps the traverse easy and quicker and also removed the
recursive, complexity of the code.

Signed-off-by: Victor Raj <victor.raj@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Leyi Rong <leyi.rong@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2019-06-28 20:31:48 +02:00
Leyi Rong
1b969112dc net/ice/base: save queue bandwidth for replay after reset
Added code to save the queue bandwidth information when it is applied
and it is replayed when queue is re-enabled again. Earlier saved value
is used for replay purpose.
Added vsi_handle, tc, and q_handle argument to the ice_cfg_q_bw_lmt,
ice_cfg_q_bw_dflt_lmt.

Signed-off-by: Tarun Singh <tarun.k.singh@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Leyi Rong <leyi.rong@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2019-06-28 20:31:48 +02:00
Qi Zhang
abd6cd540e net/ice/base: update copyright time
Update copyright time to 2019.

Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Reviewed-by: Qiming Yang <qiming.yang@intel.com>
Reviewed-by: Wenzhuo Lu <wenzhuo.lu@intel.com>
2019-03-29 17:25:31 +01:00
Qi Zhang
29a0c11489 net/ice/base: clean code
Change below function as static and also relocated code line
to align with kernel driver.

ice_aq_move_sched_elems
ice_sched_get_agg_node
ice_sched_set_node_bw_lmt
ice_sched_cfg_node_bw_alloc
ice_sched_add_agg_cfg
ice_sched_rm_agg_cfg
ice_sched_move_vsi_to_agg
ice_sched_del_rl_profile
ice_sched_rm_unused_rl_prof

Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Reviewed-by: Qiming Yang <qiming.yang@intel.com>
Reviewed-by: Wenzhuo Lu <wenzhuo.lu@intel.com>
2019-03-29 17:25:31 +01:00
Qi Zhang
ad4bd56a0d net/ice/base: add VSI queue context framework
Added code to allocate VSI queue contexts to save the queue specific
information like bandwidth etc.

Signed-off-by: Victor Raj <victor.raj@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Reviewed-by: Qiming Yang <qiming.yang@intel.com>
Reviewed-by: Wenzhuo Lu <wenzhuo.lu@intel.com>
2019-03-29 17:25:31 +01:00
Qi Zhang
6f59fc0f86 net/ice/base: add helper macros
1. Add macro ice_for_each_traffic_class to loop for each
traffic class.
2. Add macro MIN_T to wrap min with type conversion.

Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Reviewed-by: Qiming Yang <qiming.yang@intel.com>
Reviewed-by: Wenzhuo Lu <wenzhuo.lu@intel.com>
2019-03-29 17:25:31 +01:00
Qi Zhang
0c451c3198 net/ice/base: improve comments
Improve comments to follow naming rules.
Also the patch include some minor cleanup.

Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Reviewed-by: Qiming Yang <qiming.yang@intel.com>
Reviewed-by: Wenzhuo Lu <wenzhuo.lu@intel.com>
2019-03-29 17:25:31 +01:00
Paul M Stillwell Jr
93e84b1bfc net/ice/base: add basic Tx scheduler
Add code for the basic TX scheduler.

Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
2018-12-21 16:22:40 +01:00