Commit Graph

8 Commits

Author SHA1 Message Date
Rasesh Mody
ab6bf1d77a net/qede/base: restrict cache line size register padding
Add a restriction on the pad to cache line size register.

Signed-off-by: Rasesh Mody <rasesh.mody@cavium.com>
2017-10-06 02:49:48 +02:00
Rasesh Mody
2e2f392b24 net/qede/base: upgrade the FW to 8.20.0.0
This patch adds changes to upgrade to 8.20.0.0 FW.

Signed-off-by: Rasesh Mody <rasesh.mody@cavium.com>
2017-06-12 10:41:29 +01:00
Rasesh Mody
806474a684 net/qede: upgrade the FW to 8.18.9.0
This patchset adds changes to upgrade to 8.18.9.0 FW.

Signed-off-by: Rasesh Mody <rasesh.mody@cavium.com>
2017-04-04 19:02:50 +02:00
Rasesh Mody
1a998268bf net/qede/base: print various indication on Tx-timeouts
Print various indication on Tx-timeouts.

Signed-off-by: Rasesh Mody <rasesh.mody@cavium.com>
2017-04-04 19:02:49 +02:00
Rasesh Mody
f061e24d8d net/qede/base: mask Rx buffer attention bits
Mask the BRB "RC0_EOP_OUT_SYNC_FIFO_PUSH_ERROR" attention.

Signed-off-by: Rasesh Mody <rasesh.mody@cavium.com>
2017-04-04 19:02:49 +02:00
Rasesh Mody
679fe2e426 net/qede/base: fix FreeBSD build
This patch addresses compilation errors on FreeBSD with clang 3.8.0.

drivers/net/qede/base/ecore_cxt.c:1257:2: error:
     shifting a negative signed value is undefined
          SET_FIELD(cdu_params, CDUC_NCIB, elems_per_page);
          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/net/qede/base/ecore.h:82:27: note: expanded from macro 'SET_FIELD'
          (value) &= ~(name##_MASK << name##_SHIFT);
                    ~~~~~~~~~~~ ^

Fixes: ec94dbc573 ("qede: add base driver")
Cc: stable@dpdk.org

Signed-off-by: Rasesh Mody <rasesh.mody@cavium.com>
Tested-by: Andrew Rybchenko <arybchenko@solarflare.com>
2017-01-30 22:18:26 +01:00
Rasesh Mody
3cbc0bd272 net/qede/base: add HSI changes and register defines
- add the hardware software interface(HSI) changes
- add register definitions

These will be required for 8.10.9.0 FW upgrade.

Signed-off-by: Rasesh Mody <rasesh.mody@qlogic.com>
2016-10-26 19:38:29 +02:00
Rasesh Mody
ec94dbc573 qede: add base driver
The base driver is the backend module for the QLogic FastLinQ QL4xxxx
25G/40G CNA family of adapters as well as their virtual functions (VF)
in SR-IOV context.

The purpose of the base module is to:
 - provide all the common code that will be shared between the various
   drivers that would be used with said line of products. Flows such as
   chip initialization and de-initialization fall under this category.
 - abstract the protocol-specific HW & FW components, allowing the
   protocol drivers to have clean APIs, which are detached in its
   slowpath configuration from the actual Hardware Software Interface(HSI).

This patch adds a base module without any protocol-specific bits.
I.e., this adds a basic implementation that almost entirely falls under
the first category.

Signed-off-by: Harish Patil <harish.patil@qlogic.com>
Signed-off-by: Rasesh Mody <rasesh.mody@qlogic.com>
Signed-off-by: Sony Chacko <sony.chacko@qlogic.com>
2016-05-06 15:51:22 +02:00