Commit Graph

28986 Commits

Author SHA1 Message Date
Igor Romanov
aa3e21f006 common/sfc_efx/base: add ingress m-port RxQ flag
Add a flag to request support for ingress m-port on an RxQ.
Implement it only for Riverhead, other families will return an error
if the flag is set.

Signed-off-by: Igor Romanov <igor.romanov@oktetlabs.ru>
Signed-off-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
Reviewed-by: Andy Moreton <amoreton@xilinx.com>
Reviewed-by: Ivan Malov <ivan.malov@oktetlabs.ru>
2021-07-20 12:20:31 +02:00
Igor Romanov
db980d266f net/sfc: prepare for internal Tx queue
Make software index of a Tx queue and ethdev index separate.
When an ethdev TxQ is accessed in ethdev callbacks, an explicit ethdev
queue index is used.

Signed-off-by: Igor Romanov <igor.romanov@oktetlabs.ru>
Signed-off-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
Reviewed-by: Andy Moreton <amoreton@xilinx.com>
Reviewed-by: Ivan Malov <ivan.malov@oktetlabs.ru>
2021-07-20 12:20:31 +02:00
Andrew Rybchenko
704512214d net/sfc: explicitly control IRQ used for Rx queues
Interrupts support has assumptions on interrupt numbers used
for LSC and Rx queues. The first interrupt is used for LSC,
subsequent interrupts are used for Rx queues.

Signed-off-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
Reviewed-by: Andy Moreton <amoreton@xilinx.com>
2021-07-20 12:20:31 +02:00
Andrew Rybchenko
aa6dc1017c common/sfc_efx/base: support custom EvQ to IRQ mapping
Custom mapping is actually supported for EF10 and EF100 families only.

A driver (e.g. DPDK PMD) may require to customize mapping of EvQ
to interrupts if, for example, extra EvQ are used for house-keeping
in polling or wake up (via another EvQ) mode.

Signed-off-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
Reviewed-by: Andy Moreton <amoreton@xilinx.com>
2021-07-20 12:20:31 +02:00
Andrew Rybchenko
3dee345ab3 common/sfc_efx/base: separate target EvQ and IRQ config
Target EvQ and IRQ number are specified in the same location
in MCDI request. The value is treated as IRQ number if the
event queue is interrupting (corresponding flag is set) and
as target event queue otherwise.

However it is better to separate it on helper API level to
make it more clear.

Signed-off-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
Reviewed-by: Andy Moreton <amoreton@xilinx.com>
2021-07-20 12:20:31 +02:00
Andrew Rybchenko
396541fe43 net/sfc: do not enable interrupts on internal Rx queues
rxq_intr flag requests support for interrupt mode for ethdev Rx queues.
There is no internal Rx queues yet.

Signed-off-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
2021-07-20 12:20:31 +02:00
Igor Romanov
09cafbddbb net/sfc: prepare for internal Rx queue
Make software index of an Rx queue and ethdev index separate.
When an ethdev RxQ is accessed in ethdev callbacks, an explicit ethdev
queue index is used.

Signed-off-by: Igor Romanov <igor.romanov@oktetlabs.ru>
Signed-off-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
Reviewed-by: Andy Moreton <amoreton@xilinx.com>
Reviewed-by: Ivan Malov <ivan.malov@oktetlabs.ru>
2021-07-20 12:20:31 +02:00
Ali Alnubani
00b67591d2 examples/pipeline: fix build
This patch fixes the following build failures seen on Ubuntu 16.04
with gcc 5.4.0 because of uninitialized variables:
...
examples/pipeline/cli.c:1559:11: error: 'weight_val' may be used
  uninitialized in this function [-Werror=maybe-uninitialized]
...
examples/pipeline/cli.c:1545:13: error: 'member_id_val' may be used
  uninitialized in this function [-Werror=maybe-uninitialized]
...
examples/pipeline/cli.c:1538:12: error: 'group_id_val' may be used
  uninitialized in this function [-Werror=maybe-uninitialized]
...
examples/pipeline/cli.c:2189:2: error: 'idx1' may be used
  uninitialized in this function [-Werror=maybe-uninitialized]
...
examples/pipeline/cli.c:2179:43: error: 'idx0' may be used
  uninitialized in this function [-Werror=maybe-uninitialized]
...
examples/pipeline/cli.c:2265:2: error: 'idx1' may be used
  uninitialized in this function [-Werror=maybe-uninitialized]
...
examples/pipeline/cli.c:2248:43: error: 'idx0' may be used
  uninitialized in this function [-Werror=maybe-uninitialized]
...
examples/pipeline/cli.c:2358:2: error: 'idx1' may be used
  uninitialized in this function [-Werror=maybe-uninitialized]
...
examples/pipeline/cli.c:2325:43: error: 'idx0' may be used
  uninitialized in this function [-Werror=maybe-uninitialized]

Fixes: 598fe0dd0d ("examples/pipeline: support selector table")

Signed-off-by: Ali Alnubani <alialnu@nvidia.com>
Acked-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com>
2021-07-20 11:58:18 +02:00
Pavan Nikhilesh
761a321acf event/cnxk: support vectorized Tx event fast path
Add Tx event vector fastpath, integrate event vector Tx routine
into Tx burst.

Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
2021-07-16 14:16:50 +02:00
Pavan Nikhilesh
7fbbc981d5 event/cnxk: support vectorized Rx event fast path
Add Rx event vector fastpath to convert HW defined metadata into
rte_mbuf and rte_event_vector.

Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
2021-07-16 14:16:45 +02:00
Pavan Nikhilesh
072a281873 event/cnxk: support vectorized Rx adapter
Add event vector support for cnxk event Rx adapter, add control path
APIs to get vector limits and ability to configure event vectorization
on a given Rx queue.

Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
2021-07-16 14:16:44 +02:00
Pavan Nikhilesh
313e884a22 event/cnxk: support Tx adapter fast path
Add support for event eth Tx adapter fastpath operations.

Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
2021-07-16 14:16:38 +02:00
Pavan Nikhilesh
097835ecdf event/cnxk: support Tx adapter
Add support for event eth Tx adapter.

Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
2021-07-16 14:16:37 +02:00
Pavan Nikhilesh
aa4311c654 event/cnxk: support Rx adapter fast path
Add support for event eth Rx adapter fastpath operations.

Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
2021-07-16 14:16:28 +02:00
Pavan Nikhilesh
cb4bfd6e7b event/cnxk: support Rx adapter
Add support for event eth Rx adapter.
Resize cn10k workslot fastpath structure to fit in 64B cacheline size.

Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
2021-07-16 14:16:26 +02:00
Ting Xu
f5dd3ea456 net/iavf: fix bandwidth unit in TM capability query
In IAVF node TM capability querying, the unit of bandwidth is Kbps,
which is not correct according to TM specification. Change the unit to
Byte per second. Refine some unclear comments as well.

Fixes: 44d0a720a5 ("net/iavf: query QoS capabilities and set queue TC mapping")

Signed-off-by: Ting Xu <ting.xu@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2021-07-16 10:19:29 +02:00
Alvin Zhang
57e383e57f net/ice/base: support MPLS ethertype switch filter
Add MPLS training packet and offsets.
Add check to identify MPLS ethertype filters.

For example:
testpmd> flow create 0 ingress pattern eth dst is 00:11:22:33:44:55 \
         type is 0x8847 / end actions queue index 2 / end

This flow will result in all the matched ingress packets be
forwarded to queue 2.

Signed-off-by: Alvin Zhang <alvinx.zhang@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2021-07-16 10:11:30 +02:00
Simei Su
a02d9d9bae net/ice: fix ESP flow director with SPI as input set
FDIR can't work when SPI as inputset for both ESP over IP and ESP
over UDP flow. This patch fixes this issue by adding the corresponding
input set for ESP over IP and ESP over UDP when parsing input set. Also,
it adds input set bit for NAT_T_ESP to distinguish ESP over IP and ESP
over UDP.

Fixes: 70feafc1a3 ("net/ice: support ESP/NATT flow director to match outer IP")

Signed-off-by: Simei Su <simei.su@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2021-07-16 10:11:30 +02:00
Wenjun Wu
0a37b22875 net/ice/base: revert change of first profile mask
Segmentation fault mentioned in below commit is related to
other root cause under investigation.
This reverts patch below since it may have potential
risk and side effect if the first profile mask is set to 0.

Fixes: 148fdf2d35 ("net/ice/base: fix first profile mask")
Cc: stable@dpdk.org

Signed-off-by: Wenjun Wu <wenjun1.wu@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2021-07-16 10:11:30 +02:00
Joyce Kong
8649e23566 net/i40e: replace SMP barrier with thread fence in Rx
Simply replace the SMP barrier with atomic thread fence for
i40e hw ring scan, if there is no synchronization point.

Signed-off-by: Joyce Kong <joyce.kong@arm.com>
Reviewed-by: Ruifeng Wang <ruifeng.wang@arm.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2021-07-16 10:11:30 +02:00
Wenjun Wu
9e29a278bc net/iavf: support default RSS for IP fragment
This patch adds default RSS support for IPv4 and IPv6 fragment packet.

Signed-off-by: Wenjun Wu <wenjun1.wu@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2021-07-16 10:11:30 +02:00
Lingyu Liu
36c2b46fed net/iavf: support RSS for GTPoGRE
Support AVF RSS for inner most header of GTPoGRE packet. It supports
RSS based on inner most IP src + dst address and TCP/UDP src + dst
port.

Signed-off-by: Lingyu Liu <lingyu.liu@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2021-07-16 10:11:30 +02:00
Lingyu Liu
71d3c57eae net/iavf: support flow director for GTPoGRE
Support AVF FDIR for inner header of GTPoGRE tunnel packet.
Only patterns without inner most L3,L4 header support outer L3 src/dst
and TEID,QFI FDIR.

+------------------------------------+-------------------------------+
|                Pattern             |            Input Set          |
+------------------------------------+-------------------------------+
|eth/ipv4/gre/ipv4/gtpu/(eh/)ipv4    |inner: src/dst ip              |
|eth/ipv4/gre/ipv4/gtpu/(eh/)ipv4/udp|inner: src/dst ip, src/dst port|
|eth/ipv4/gre/ipv4/gtpu/(eh/)ipv4/tcp|inner: src/dst ip, src/dst port|
|eth/ipv4/gre/ipv4/gtpu/(eh/)ipv6    |inner: src/dst ip              |
|eth/ipv4/gre/ipv4/gtpu/(eh/)ipv6/udp|inner: src/dst ip, src/dst port|
|eth/ipv4/gre/ipv4/gtpu/(eh/)ipv6/tcp|inner: src/dst ip, src/dst port|
|eth/ipv4/gre/ipv6/gtpu/(eh/)ipv4    |inner: src/dst ip              |
|eth/ipv4/gre/ipv6/gtpu/(eh/)ipv4/udp|inner: src/dst ip, src/dst port|
|eth/ipv4/gre/ipv6/gtpu/(eh/)ipv4/tcp|inner: src/dst ip, src/dst port|
|eth/ipv4/gre/ipv6/gtpu/(eh/)ipv6    |inner: src/dst ip              |
|eth/ipv4/gre/ipv6/gtpu/(eh/)ipv6/udp|inner: src/dst ip, src/dst port|
|eth/ipv4/gre/ipv6/gtpu/(eh/)ipv6/tcp|inner: src/dst ip, src/dst port|
|eth/ipv6/gre/ipv4/gtpu/(eh/)ipv4    |inner: src/dst ip              |
|eth/ipv6/gre/ipv4/gtpu/(eh/)ipv4/udp|inner: src/dst ip, src/dst port|
|eth/ipv6/gre/ipv4/gtpu/(eh/)ipv4/tcp|inner: src/dst ip, src/dst port|
|eth/ipv6/gre/ipv4/gtpu/(eh/)ipv6    |inner: src/dst ip              |
|eth/ipv6/gre/ipv4/gtpu/(eh/)ipv6/udp|inner: src/dst ip, src/dst port|
|eth/ipv6/gre/ipv4/gtpu/(eh/)ipv6/tcp|inner: src/dst ip, src/dst port|
|eth/ipv6/gre/ipv6/gtpu/(eh/)ipv4    |inner: src/dst ip              |
|eth/ipv6/gre/ipv6/gtpu/(eh/)ipv4/udp|inner: src/dst ip, src/dst port|
|eth/ipv6/gre/ipv6/gtpu/(eh/)ipv4/tcp|inner: src/dst ip, src/dst port|
|eth/ipv6/gre/ipv6/gtpu/(eh/)ipv6    |inner: src/dst ip              |
|eth/ipv6/gre/ipv6/gtpu/(eh/)ipv6/udp|inner: src/dst ip, src/dst port|
|eth/ipv6/gre/ipv6/gtpu/(eh/)ipv6/tcp|inner: src/dst ip, src/dst port|
|eth/ipv4/gre/ipv4/gtpu(/eh)         |outer: src/dst ip, teid(,qfi)  |
|eth/ipv4/gre/ipv6/gtpu(/eh)         |outer: src/dst ip, teid(,qfi)  |
|eth/ipv6/gre/ipv4/gtpu(/eh)         |outer: src/dst ip, teid(,qfi)  |
|eth/ipv6/gre/ipv6/gtpu(/eh)         |outer: src/dst ip, teid(,qfi)  |
+------------------------------------+-------------------------------+

Signed-off-by: Lingyu Liu <lingyu.liu@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2021-07-16 10:11:30 +02:00
Lingyu Liu
b3025311cd net/iavf: support flow pattern for GTPoGRE
Add GTPoGRE pattern support for AVF FDIR and RSS.

Signed-off-by: Lingyu Liu <lingyu.liu@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2021-07-16 10:11:30 +02:00
Ajit Khaparde
7962fd44c8 net/bnxt: update CFA resource types
Update cfa_resource_types.h to add a new entry for compatibility with FW.

Signed-off-by: Shuanglin Wang <shuanglin.wang@broadcom.com>
Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com>
Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
2021-07-16 05:44:49 +02:00
Kalesh AP
84fd852caa net/bnxt: clear cached statistics
As part of the workaround put in the commit "219842b9990c",
driver caches the last read stats values from the hardware.
But this is not cleared during the clear stats operation. This
results in showing up stale stats values while reading the stats
after the clear operation.

Fixes: 219842b999 ("net/bnxt: workaround spurious zero stats in Thor")
Cc: stable@dpdk.org

Signed-off-by: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Reviewed-by: Lance Richardson <lance.richardson@broadcom.com>
Reviewed-by: Somnath Kotur <somnath.kotur@broadcom.com>
2021-07-15 02:31:32 +02:00
Somnath Kotur
95de0faf12 net/bnxt: handle pause storm event
FW has been modified to send a new async event when it detects
a pause storm. Register for this new event and log it upon receipt.

Signed-off-by: Somnath Kotur <somnath.kotur@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
2021-07-14 20:29:05 +02:00
Somnath Kotur
1125b16bf6 net/bnxt: refactor async event handling
Store the async event completion data1 and data2 in separate variables
at the start of the function before the switch case for the different
events so they can be used by any of the event handlers.

Signed-off-by: Somnath Kotur <somnath.kotur@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
2021-07-14 20:29:05 +02:00
Kalesh AP
8fd709a10b net/bnxt: inform firmware about host MTU
This enables device firmware to respond appropriately to BMC queries
about the driver's configured MTU.

Signed-off-by: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Reviewed-by: Lance Richardson <lance.richardson@broadcom.com>
2021-07-14 20:29:05 +02:00
Kalesh AP
89e6a0c0da net/bnxt: update HSI structure
- HWRM version updated to 1.10.2.44
- Added corresponding driver changes for the Admin MTU field name change.

Signed-off-by: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Reviewed-by: Somnath Kotur <somnath.kotur@broadcom.com>
2021-07-14 20:29:05 +02:00
Weifeng Li
8117f5f61a net/bnxt: fix nested lock during bonding
Bnxt PMD registers LSC callback (bond_ethdev_lsc_event_callback) when
working at bond mode. This callback will dead lock when LSC
interrupt triggered.

lsc interrupt ->
bnxt_handle_async_event ->
bnxt_link_update_op ->
bond_ethdev_lsc_event_callback (lsc_lock) ->
bnxt_link_update_op ->
bond_ethdev_lsc_event_callback (lsc_lock dead lock)

Fixes: c2faa1d196 ("net/bnxt: add support for LSC interrupt event")
Cc: stable@dpdk.org

Signed-off-by: Weifeng Li <liweifeng96@126.com>
Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
2021-07-13 06:19:11 +02:00
Lance Richardson
5ed30db87f net/bnxt: fix missing barriers in completion handling
Ensure that Rx/Tx/Async completion entry fields are accessed
only after the completion's valid flag has been loaded and
verified. This is needed for correct operation on systems that
use relaxed memory consistency models.

Fixes: 2eb53b134a ("net/bnxt: add initial Rx code")
Fixes: 6eb3cc2294 ("net/bnxt: add initial Tx code")
Cc: stable@dpdk.org

Signed-off-by: Lance Richardson <lance.richardson@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Reviewed-by: Ruifeng Wang <ruifeng.wang@arm.com>
2021-07-12 20:38:12 +02:00
Satheesh Paul
1c3b657a6a net/cnxk: support raw flow pattern
Add support for rte_flow_item_raw to parse custom L2 and L3
protocols.

Signed-off-by: Satheesh Paul <psatheesh@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
2021-07-13 12:19:22 +02:00
Satheesh Paul
612ce5cf7d common/cnxk: support custom L2/L3 protocols parsing
Add roc API for parsing custom L2 and L3 protocols.

Signed-off-by: Satheesh Paul <psatheesh@marvell.com>
Reviewed-by: Kiran Kumar K <kirankumark@marvell.com>
2021-07-13 12:17:51 +02:00
Satha Rao
e7bbbcb26f net/cnxk: update link status when device stopped
Set link status to down and don't fetch link status from kernel
when device in stopped state.

Signed-off-by: Satha Rao <skoteshwar@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
2021-07-13 11:29:49 +02:00
Satha Rao
d9dda782ac net/octeontx2: fix TM node statistics query
Until hierarchy committed TM hardware resources are not allocated
for node.
This patch check for status of HW resources before reading statistics.

Fixes: 1e25d57fae ("net/octeontx2: add TM stats and shaper profile")
Cc: stable@dpdk.org

Signed-off-by: Satha Rao <skoteshwar@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
2021-07-13 11:29:11 +02:00
Satha Rao
12e491a6b6 net/octeontx2: handle link status when device stopped
Set link status to down and don't fetch link status from kernel
when device in stopped state.

Signed-off-by: Satha Rao <skoteshwar@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
2021-07-13 11:29:10 +02:00
Satheesh Paul
d81cea5280 net/cnxk: fix default MCAM allocation size
Preallocation of MCAM entries is not valid anymore since the
AF side MCAM allocation scheme has changed. This patch disables
preallocation by changing the default MCAM preallocation size
from 8 to 1.

Fixes: 168c59cfe4 ("net/octeontx2: add flow MCAM utility functions")
Cc: stable@dpdk.org

Signed-off-by: Satheesh Paul <psatheesh@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
2021-07-12 14:44:20 +02:00
Anoob Joseph
ec8f303c65 net/octeontx2: support non-ethernet L2 header
In the inline inound path, a custom header would be present at L3 which
has sequence number & SPI. L2 need to be adjusted such that the eventual
packet would have L3 after L2. Remove assumption of L2 type in this
handling.

Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
2021-07-12 14:04:42 +02:00
Meir Levi
71c5085bfb net/mvpp2: fix not supported VLAN operations status
vlan_strip and vlan_extend features need to return "unsupported"
error value.

Fixes: ff0b8b10dc ("net/mvpp2: support VLAN offload")
Cc: stable@dpdk.org

Signed-off-by: Meir Levi <mlevi4@marvell.com>
Reviewed-by: Liron Himi <lironh@marvell.com>
2021-07-12 11:07:08 +02:00
Dana Vardi
e622c1a88e net/mvpp2: fix configured state dependency
Need to set configure flag to allow create and commit mrvl tm
hierarchy tree. tm configuration depends on parameters that are
being set in port configure stage, e.g. nb_tx_queues.
This also aligned with the tm api description.

Fixes: 429c394417 ("net/mvpp2: support traffic manager")
Cc: stable@dpdk.org

Signed-off-by: Dana Vardi <danat@marvell.com>
Reviewed-by: Liron Himi <lironh@marvell.com>
2021-07-12 10:31:21 +02:00
Dana Vardi
8fa07a68a6 net/mvpp2: fix port speed overflow
ethtool_cmd_speed return uint32 and after the arithmetic
operation in mrvl_get_max_rate func the result is out of range.

Fixes: 429c394417 ("net/mvpp2: support traffic manager")
Cc: stable@dpdk.org

Signed-off-by: Dana Vardi <danat@marvell.com>
Reviewed-by: Liron Himi <lironh@marvell.com>
2021-07-12 09:59:52 +02:00
Sarosh Arif
6e695b0cda net/mlx5: fix typo in vectorized Rx comments
Change "returing" to "returning".

Fixes: 2e542da709 ("net/mlx5: add Altivec Rx")
Fixes: 570acdb1da ("net/mlx5: add vectorized Rx/Tx burst for ARM")
Fixes: 3c2ddbd413 ("net/mlx5: separate shareable vector functions")
Cc: stable@dpdk.org

Signed-off-by: Sarosh Arif <sarosh.arif@emumba.com>
2021-07-15 16:32:09 +02:00
Alexander Kozyrev
acc8747953 net/mlx5: fix threshold for mbuf replenishment in MPRQ
The replenishment scheme for the vectorized MPRQ Rx burst aims
to improve the cache locality by allocating new mbufs only when
there are almost no mbufs left: one burst gap between allocated
and consumed indexes.

This gap is not big enough to accommodate a corner case when we
have a very aggressive CQE compression with multiple regular CQEs
at the beginning and 64 zipped CQEs at the end.

Need to keep in mind this case and extend the replenishment
threshold by MLX5_VPMD_RX_MAX_BURST (64) to avoid mbuf overflow.

Fixes: 5fc2e5c27d ("net/mlx5: fix mbuf overflow in vectorized MPRQ")
Cc: stable@dpdk.org

Signed-off-by: Alexander Kozyrev <akozyrev@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
2021-07-15 16:22:27 +02:00
Xiaoyu Min
0ed93c1344 net/mlx5: fix missing RSS expansion of IPv6 frag
IPV6_FRAG_EXT item is missed for RSS expansion which causes wrongly
expanded flows:
flow create 0 ingress pattern eth / ipv6 / udp dst is 250 / vxlan-gpe /
ipv6 / ipv6_frag_ext / end actions rss level 2 types ip end / end

Different from other items, IPV6_FRAG_EXT hasn't next field because HW
only support to do hash of UDP/TCP for non-fragment.

This MLX5_EXPANSION_IPV6_FRAG_EXT node in RSS expansion graph only helps
RSS expansion function to locate right node in graph from which start
to expand.

Fixes: 0e5a0d8f75 ("net/mlx5: support match on IPv6 fragment extension")
Cc: stable@dpdk.org

Signed-off-by: Xiaoyu Min <jackmin@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
2021-07-15 16:22:26 +02:00
Xiaoyu Min
1c4f7044c6 net/mlx5: fix missing RSS expandable items
Some RSS expandable items are missing which leads to the expanded
rte flow rules with wrong patterns.

Fix by adding missed items.

Fixes: d91093b9a2 ("net/mlx5: fix RSS pattern expansion")
Cc: stable@dpdk.org

Signed-off-by: Xiaoyu Min <jackmin@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
2021-07-15 16:22:25 +02:00
Gregory Etelson
c410e1d562 net/mlx5: support flow matchng on IPv4 IHL
Query MLX5 port hardware if it is capable to offload IPv4
IHL field.

Provide flow rules capability to match on IPv4 IHL field.
Minimal HCA firmware version required to offload IPv4 IHL is
xx_30_2000.

Signed-off-by: Gregory Etelson <getelson@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
2021-07-15 16:22:20 +02:00
Suanming Mou
9e22b859cd doc: add multi-thread flow rate optimizations for mlx5
This commit adds the multiple-thread flow insertion optimization
description.

Signed-off-by: Suanming Mou <suanmingm@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
2021-07-15 16:16:18 +02:00
Suanming Mou
a5835d530f net/mlx5: optimize Rx queue match
As hrxq struct has the indirect table pointer, while matching the
hrxq, better to use the hrxq indirect table instead of searching
from the list.

This commit optimizes the hrxq indirect table matching.

Signed-off-by: Suanming Mou <suanmingm@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
2021-07-15 16:09:23 +02:00
Suanming Mou
cde19e8634 net/mlx5: change memory release configuration
This commit changes the index pool memory release configuration
to 0 when memory reclaim mode is not required.

Signed-off-by: Suanming Mou <suanmingm@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
2021-07-15 16:09:22 +02:00