Currently, it is not possible to check support for intrinsics that
are platform-specific, cannot be abstracted in a generic way, or do not
have support on all architectures. The CPUID flags can be used to some
extent, but they are only defined for their platform, while intrinsics
will be available to all code as they are in generic headers.
This patch introduces infrastructure to check support for certain
platform-specific intrinsics, and adds support for checking support for
IA power management-related intrinsics for UMWAIT/UMONITOR and TPAUSE.
Signed-off-by: Anatoly Burakov <anatoly.burakov@intel.com>
Signed-off-by: Liang Ma <liang.j.ma@intel.com>
Acked-by: David Christensen <drc@linux.vnet.ibm.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Acked-by: Ruifeng Wang <ruifeng.wang@arm.com>
Acked-by: Ray Kinsella <mdr@ashroe.eu>
Add a new CPUID flag indicating processor support for UMONITOR/UMWAIT
and TPAUSE instructions instruction.
Signed-off-by: Liang Ma <liang.j.ma@intel.com>
Signed-off-by: Anatoly Burakov <anatoly.burakov@intel.com>
Acked-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
This patch adds CPU flags which will enable the detection of ISA
features available on more recent x86 based CPUs.
The CPUID leaf information can be found in
Table 1-2. "Information Returned by CPUID Instruction" of this document:
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
The following CPU flags are added in this patch:
- AVX-512 doubleword and quadword instructions.
- AVX-512 integer fused multiply-add instructions.
- AVX-512 conflict detection instructions.
- AVX-512 byte and word instructions.
- AVX-512 vector length instructions.
- AVX-512 vector bit manipulation instructions.
- AVX-512 vector bit manipulation 2 instructions.
- Galois field new instructions.
- Vector AES instructions.
- Vector carry-less multiply instructions.
- AVX-512 vector neural network instructions.
- AVX-512 for bit algorithm instructions.
- AVX-512 vector popcount instructions.
- Cache line demote instructions.
- Direct store instructions.
- Direct store 64B instructions.
- AVX-512 two register intersection instructions.
Signed-off-by: Kevin Laatz <kevin.laatz@intel.com>
Acked-by: Harry van Haaren <harry.van.haaren@intel.com>
Acked-by: Ray Kinsella <mdr@ashroe.eu>
The arch-specific directories arm, ppc and x86 in common/arch/
are moved at the same level as the OS-specific directories.
It makes more clear that EAL is covering a matrix combining OS and arch.
Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
Reviewed-by: David Christensen <drc@linux.vnet.ibm.com>
Acked-by: David Marchand <david.marchand@redhat.com>
