Rx event on Riverhead provides a number of received packets and
no classification/offloads information is available Rx event.
Introduce a new event callback to be implemented by drivers.
The callback provides information about the number of completed
packets. libefx-based drivers should implement the new callback
for Riverhead and keep the old one for Siena and EF10 NICs.
The new callback may be used for Medford2 NO_CONT_EV Rx mode
support.
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
Reviewed-by: Andy Moreton <amoreton@xilinx.com>
Rx/Tx queue DMA sync should not assume descriptor size to be the same
for all NIC familties since it Tx descritor size is 16 on Riverhead.
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
Reviewed-by: Andy Moreton <amoreton@xilinx.com>
Tx control path on Riverhead is very similar to EF10, but datapath
differs a lot since Tx descriptor size is 16 bytes (vs 8 bytes on EF10).
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
Reviewed-by: Andy Moreton <amoreton@xilinx.com>
Reuse EF10 RSS-related functions since current version of the RSS
interface is compatible with EF10.
Implement own functions to create and destroy Rx queues which reuse
MCDI wrappers which are shared with EF10.
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
Reviewed-by: Andy Moreton <amoreton@xilinx.com>
Make NIC family specific functions a bit shorter and reduce
code duplication.
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
Reviewed-by: Andy Moreton <amoreton@xilinx.com>
Rx queue structure is allocated in generic code, but was freed in NIC
family specific callbacks. Move free to generic function makes NIC
family specific callbacks shorter and reduces code duplication.
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
Reviewed-by: Andy Moreton <amoreton@xilinx.com>
The counter is incremented in generic efx_rx_qcreate(), but was
asserted and decremented in NIC family specific queue create and
destroy callbacks. Move assert and decrement to generic functions
as well to make NIC family specific callbacks shorter.
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
Reviewed-by: Andy Moreton <amoreton@xilinx.com>
Extended version of MCDI allows up to 64 DMA addresses which are
required for Riverhead.
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
Reviewed-by: Andy Moreton <amoreton@xilinx.com>
TxQ init/fini MCDI is similar on Riverhead and these
functions should be reused to implement TxQ creation and
destruction on Riverhead.
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
Reviewed-by: Andy Moreton <amoreton@xilinx.com>
Reviewed-by: Vijay Kumar Srivastava <vsrivast@xilinx.com>
RxQ init/fini MCDI is similar on Riverhead and these
functions should be reused to implement RxQ creation and
destruction on Riverhead.
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
Reviewed-by: Andy Moreton <amoreton@xilinx.com>
EF100 MCDI event layout is same as on EF10 except added QDMA phase
bit which is unused on EF10.
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
Reviewed-by: Andy Moreton <amoreton@xilinx.com>
Client drivers relying on interrupts will fail to complete event
queue creation on Riverhead boards as the latter have no support
for INIT_DONE events which means that it's useless to wait until
initialisation callback is triggered by interrupt-driven polling.
Client drivers which avoid interrupt-driven polling still handle
INIT_DONE events by direct polling and will fail to do so.
Solve this problem by adding an extra poll-once method which
will be called by client drivers after queue creation (probably,
with driver-specific lock being held). The method will invoke
initialisation callback on Riverhead and do nothing on the other
boards. Then the drivers will proceed with normal waiting which
will complete immediately in the case of Riverhead.
Signed-off-by: Ivan Malov <ivan.malov@oktetlabs.ru>
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
Reviewed-by: Andy Moreton <amoreton@xilinx.com>
Events are significantly reworked on Riverhead, so it is better
to implement own set of callbacks to simplify future development
and avoid inheritance of legacy code.
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
Reviewed-by: Andy Moreton <amoreton@xilinx.com>
The decision on which version of the INIT_EVQ command to use may
be done inside the function itself. Caller should just provide
enough information sufficient in both cases. It avoids code
duplication and simplifies maintenance.
If v2 is not supported, keep decision about low-latency hint outside
the MCDI helper function since it will differ on Riverhead (there is
no EVB yet, but still want merging for better throughput).
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
Reviewed-by: Andy Moreton <amoreton@xilinx.com>
v1 and v2 defines are the same except output length.
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
Reviewed-by: Andy Moreton <amoreton@xilinx.com>
There is no point to duplicate these generic checks in NIC family
specific handlers.
As the side effect it fixes bug with incorrect interrupt moderation
settings silently ignored on event queue create on Siena.
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
Reviewed-by: Andy Moreton <amoreton@xilinx.com>
Reviewed-by: Vijay Kumar Srivastava <vsrivast@xilinx.com>
EvQ init/fini MCDI is similar on Riverhead and these
functions should be reused to implement EvQ creation and
destruction on Riverhead.
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
Reviewed-by: Andy Moreton <amoreton@xilinx.com>
Reviewed-by: Vijay Kumar Srivastava <vsrivast@xilinx.com>
Riverhead supports interrupt aggregation rings. Right now there
are no plans to support it in libefx, but it is better to have
own set of callbacks to easier handle EF10 and Riverhead
differences in the future.
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
Reviewed-by: Andy Moreton <amoreton@xilinx.com>
There is no difference yet in MAC support on EF10 and Riverhead.
So, it is better to reuse existing methods.
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
Reviewed-by: Andy Moreton <amoreton@xilinx.com>
Reviewed-by: Vijay Kumar Srivastava <vsrivast@xilinx.com>
Filtering MCDI on Riverhead are the same as on EF10.
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
Reviewed-by: Andy Moreton <amoreton@xilinx.com>
Reviewed-by: Vijay Kumar Srivastava <vsrivast@xilinx.com>
Define basic NIC features and limitations.
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
Reviewed-by: Andy Moreton <amoreton@xilinx.com>
Reviewed-by: Vijay Kumar Srivastava <vsrivast@xilinx.com>
There is no point to duplicate it NIC family specific probe handlers.
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
Reviewed-by: Andy Moreton <amoreton@xilinx.com>
ef10_get_datapath_caps() should simply fill in NIC configuration
based MC_CMD_GET_CAPABILITIES output.
Number of PFs is a part of board configuration should be obtained
in corresponding function.
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
Reviewed-by: Andy Moreton <amoreton@xilinx.com>
The function which gets capabilities from MC should simply fill in
NIC configuration. Caller should decide if the configuration is
supported or not.
The change is required to prepare the function to be reused on
Riverhead.
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
Reviewed-by: Andy Moreton <amoreton@xilinx.com>
There is no difference yet in PHY support on EF10 and Riverhead.
So, it is better to reuse existing methods.
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
Reviewed-by: Andy Moreton <amoreton@xilinx.com>
Reviewed-by: Vijay Kumar Srivastava <vsrivast@xilinx.com>
MCDI on Riverhead is very close to the EF10 and there is no
point to duplicate the code.
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
Reviewed-by: Andy Moreton <amoreton@xilinx.com>
Riverhead family got letter 'G' for registers definition.
Registers used for Riverhead should have the letter in the
specification range.
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
Reviewed-by: Andy Moreton <amoreton@xilinx.com>
Reviewed-by: Vijay Kumar Srivastava <vsrivast@xilinx.com>
Riverhead is the first NIC family of the EF100 architecture.
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
Reviewed-by: Andy Moreton <amoreton@xilinx.com>
Reviewed-by: Vijay Kumar Srivastava <vsrivast@xilinx.com>
Event queue host interface differ on Riverhead and implementation
will be different.
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
Reviewed-by: Andy Moreton <amoreton@xilinx.com>
Adding support for VLAN based RSS hash. Two bytes of TCI field
will be considered for hashing.
Signed-off-by: Kiran Kumar K <kirankumark@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Replace mmap() and munmap() APIs with EAL abstraction for the same.
Fixes: e1d9a02ad8 ("common/octeontx2: introduce common device class")
Cc: stable@dpdk.org
Signed-off-by: Sarosh Arif <sarosh.arif@emumba.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Update mail box data structures to sync with af driver mbox
changes done to retrieve VF's base steering rule.
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Signed-off-by: Harman Kalra <hkalra@marvell.com>
These helper will be reused by other libefx consumers, e.g. vDPA
driver.
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
Reviewed-by: Andy Moreton <amoreton@xilinx.com>
Move libefx (base driver) into common driver.
Prepare to add vDPA driver which will use the common driver as well.
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
Reviewed-by: Andy Moreton <amoreton@xilinx.com>
Since the 20.08 release deprecated rte_cio_*mb APIs because these APIs
provide the same functionality as rte_io_*mb APIs on all platforms, so
remove them and use rte_io_*mb instead.
Signed-off-by: Phil Yang <phil.yang@arm.com>
Signed-off-by: Joyce Kong <joyce.kong@arm.com>
Reviewed-by: Ruifeng Wang <ruifeng.wang@arm.com>
Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
Acked-by: David Marchand <david.marchand@redhat.com>
Before this commit system call memalign was used for aligned
allocations, however memalign is deprecated.
Based on (1) - POSIX requires that memory aligned allocations can be
freed using free. Some systems provide no way to reclaim memory
allocated with memalign (because one can only pass to free a pointer
gotten from malloc, while, memalign would call malloc and then align the
obtained value).
Another issue is that 64/32 bits architectures use a minimal alignment
size. So any requested alignment below the minimal system size can be
simplified by calling malloc.
The glibc implementation allows memory obtained from posix_memalign to
be reclaimed with free. This commit replaces system call memalign with
system call posix_memalign. It also calls malloc in case the requested
alignment is below the minimal system size.
(1) https://linux.die.net/man/3/memalign
Fixes: d38e3d5266 ("common/mlx5: add memory management functions")
Cc: stable@dpdk.org
Signed-off-by: Ophir Munk <ophirmu@nvidia.com>
Acked-by: Matan Azrad <matan@mellanox.com>
Some IPv6 prefix related protocol header fields are defined in this
patch, so that we can use prefix instead of full IPv6 address for RSS.
Ref https://tools.ietf.org/html/rfc6052.
Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Beilei Xing <beilei.xing@intel.com>
Most values from the VIRTCHNL_OP_GET_VF_RESOURCES are stored in the
iavf_hw_capabilities structure. Unfortunately, it seems that
max_mtu was missed. Add this member to the structure and save it when
parsing hw config.
Signed-off-by: Brett Creeley <brett.creeley@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Beilei Xing <beilei.xing@intel.com>
1. use BIT to replace <<
2. move VIRTCHNL_VF_CAP_DCF to keep order
3. align the vc msg validate
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Beilei Xing <beilei.xing@intel.com>
Currently, there is no way for a VF driver to specify that it wants to
change its device/primary unicast MAC address. This makes it
difficult/impossible for the PF driver to track the VF's device/primary
unicast MAC address, which is used for VM/VF reboot and displaying on
the host. Fix this by using 2 bits of a pad byte in the
virtchnl_ether_addr structure so the VF can specify what type of MAC
it's adding/deleting.
Below are the values that should be used by all VF drivers going
forward.
VIRTCHNL_ETHER_ADDR_LEGACY(0):
- The type should only ever be 0 for legacy AVF drivers (i.e.
drivers that don't support the new type bits). The PF drivers
will track VF's device/primary unicast MAC using with best
effort.
VIRTCHNL_ETHER_ADDR_PRIMARY(1):
- This type should only be used when the VF is changing their
device/primary unicast MAC. It should be used for both delete
and add cases related to the device/primary unicast MAC.
VIRTCHNL_ETHER_ADDR_EXTRA(2):
- This type should be used when the VF is adding and/or deleting
MAC addresses that are not the device/primary unicast MAC. For
example, extra unicast addresses and multicast addresses
assuming the PF supports "extra" addresses at all.
If a PF is parsing the type field of the virtchnl_ether_addr, then it
should use the VIRTCHNL_ETHER_ADDR_TYPE_MASK to mask the first two bits
of the type field since 0, 1, and 2 are the only valid values.
Signed-off-by: Brett Creeley <brett.creeley@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Beilei Xing <beilei.xing@intel.com>
According to ABI policy, the internal functions should have the new tag
__rte_internal and linked into INTERNAL sessions.
Signed-off-by: Haiyue Wang <haiyue.wang@intel.com>
Acked-by: Beilei Xing <beilei.xing@intel.com>
Acked-by: Ferruh Yigit <ferruh.yigit@intel.com>
Several DV-based structs of type 'struct mlx5dv_devx_XXX' are replaced
with 'void *' to enable compilation under non-Linux operating systems.
New getter functions were added to retrieve the specific fields that
were previously accessed directly.
Replaced structs:
'struct mlx5dv_pp *'
'struct mlx5dv_devx_event_channel *'
'struct mlx5dv_devx_umem *'
'struct mlx5dv_devx_uar *'
Signed-off-by: Ophir Munk <ophirmu@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
Enumerated variable REG_NONE (defined in mlx5_prm.h) is in conflict with
Windows definition (winnt.h): #define REG_NONE ( 0ul ) // No value type
To enable mlx5 PMD Windows compilation - rename REG_NONE as REG_NON.
Signed-off-by: Ophir Munk <ophirmu@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
strsep() is a non-standardized API (by C or POSIX) and thus it is
non-portable between different operating systems. Replace it with
strtok_r() which is standardized by the C standard, and hence also by
POSIX.
The replacement occurs in the code that extracts individual PCI class
names (e.g. class=net:vdpa:foo:bar).
Signed-off-by: Ophir Munk <ophirmu@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
Remove the deprecated buf_physaddr union field from rte_mbuf.
It is replaced with buf_iova which is at the same offset.
The single field buf_physaddr in rte_kni_mbuf is also renamed.
This concludes a 3-year process of semantic change.
Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
Acked-by: Andrew Rybchenko <arybchenko@solarflare.com>
Acked-by: Ray Kinsella <mdr@ashroe.eu>
Remove the deprecated functions
- rte_mbuf_data_dma_addr
- rte_mbuf_data_dma_addr_default
which aliased the more recent functions
- rte_mbuf_data_iova
- rte_mbuf_data_iova_default
Remove the deprecated macros
- rte_pktmbuf_mtophys
- rte_pktmbuf_mtophys_offset
which aliased the more recent macros
- rte_pktmbuf_iova
- rte_pktmbuf_iova_offset
Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
Acked-by: Andrew Rybchenko <arybchenko@solarflare.com>
Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>
Acked-by: Ray Kinsella <mdr@ashroe.eu>
Remove the deprecated unioned fields phys_addr
from the structures rte_memseg and rte_memzone.
They are replaced with the fields iova which are at the same offsets.
Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
Acked-by: Andrew Rybchenko <arybchenko@solarflare.com>
Acked-by: Anatoly Burakov <anatoly.burakov@intel.com>
Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>
Acked-by: Ray Kinsella <mdr@ashroe.eu>
A decision was made [1] to no longer support Make in DPDK, this patch
removes all Makefiles that do not make use of pkg-config, along with
the mk directory previously used by make.
[1] https://mails.dpdk.org/archives/dev/2020-April/162839.html
Signed-off-by: Ciara Power <ciara.power@intel.com>
Reviewed-by: Ruifeng Wang <ruifeng.wang@arm.com>
Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
Start a new release cycle with empty release notes.
The ABI version becomes 21.0.
The ABI major is back to normal, having only one number (21 vs 20.0).
The map files are updated to the new ABI major number (21).
The ABI exceptions are dropped.
Travis ABI check is disabled because compatibility is not preserved.
Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
Acked-by: Ray Kinsella <mdr@ashroe.eu>
Reserved field should be 0x60 instead of 0x40.
Will fail FW check otherwise.
Fixes: 9428310ae1 ("regex/mlx5: add engine status check")
Signed-off-by: Yuval Avnery <yuvalav@mellanox.com>
Acked-by: Ori Kam <orika@mellanox.com>
mlx5_nl_mac_addr_flush should flush all allocated MAC
addresses.
The MAC addresses array size should be of size
MLX5_MAX_MAC_ADDRESSES, but currently we return without
flushing the addresses if size is MLX5_MAX_MAC_ADDRESSES.
This was fixed by not allowing an array larger than
MLX5_MAX_MAC_ADDRESSES.
Fixes: e9a8ac59b6 ("common/mlx5: fix MAC addresses assert")
Cc: stable@dpdk.org
Signed-off-by: Shiri Kuzin <shirik@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
To detect the timestamp mode configured on the NIC the mlx5
PMD uses the firmware command ACCESS_REGISTER_USER. This
command is relatively new and might be not supported by
older firmware versions and was rejected, causing annoying
messages in kernel log.
This patch adds the attribute flag check whether firmware
supports the command and avoid the call if it does not.
Fixes: bb7ef9a962 ("common/mlx5: add register access DevX routine")
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Currently, the counter query requires the counter ID should start
with 4 aligned. In none-batch mode, the counter pool might have the
chance to get the counter ID not 4 aligned. In this case, the counter
should be skipped, or the query will be failed.
Skip the counter with ID not 4 aligned as the first counter in the
none-batch count pool to avoid invalid counter query. Once having
new min_dcs ID in the poll less than the skipped counters, the
skipped counters will be returned to the pool free list to use.
Fixes: 5382d28c21 ("net/mlx5: accelerate DV flow counter transactions")
Cc: stable@dpdk.org
Signed-off-by: Suanming Mou <suanmingm@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
When Rx/Tx queue was being created with DevX the allocated
doorbell record size was only uint64_t. That was definitely
less than size of CPU cacheline and it might have happened the
doorbell records attached to different queues handled by
different cores were allocated within same cacheline. It might
have caused the contention on doorbell record writing.
This patch extends the allocated memory size for doorbell
record to cacheline size.
Fixes: 21cae8580f ("net/mlx5: allocate door-bells via DevX")
Cc: stable@dpdk.org
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
This adds pci detection and documentation for Intel GEN2
QuickAssist device 200xx (PF Did 0x18ee, VF Did 0x18ef).
Signed-off-by: Adam Dybkowski <adamx.dybkowski@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>
This patch fixes the uninitialized variable bug in QAT PMD.
Fixes: 9f27a860dc ("crypto/qat: move generic qp function to qp file")
Cc: stable@dpdk.org
Signed-off-by: Adam Dybkowski <adamx.dybkowski@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>
This patch removes unused fields from structs qat_qp and
qat_qp_config, together with their initializations.
Signed-off-by: Adam Dybkowski <adamx.dybkowski@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>
The structure cpt_request_info needs only 8 byte alignment.
This patch replaces __rte_cache_aligned of cpt_request_info
with __rte_aligned(8) and removes __rte_aligned(8) in
cpt_meta_info structure.
Fixes: fab634eb87 ("crypto/octeontx2: support security session data path")
Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
Acked-by: Anoob Joseph <anoobj@marvell.com>
DOCSIS protocol performance in the downlink direction can be improved
significantly in the QAT SYM PMD, especially for larger packets, by
pre-processing all CRC generations in a batch before building and
enqueuing any requests to the HW. This patch adds this optimization.
Fixes: 6f0ef23740 ("crypto/qat: support DOCSIS protocol")
Signed-off-by: David Coyle <david.coyle@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>
Now that mlx5_pci PMD checks for enabled classes and performs
probe(), remove() of associated classes, individual class driver
does not need to check if other driver is enabled.
Signed-off-by: Parav Pandit <parav@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
Add generic mlx5 PCI PMD layer as part of existing common_mlx5
module. This enables multiple classes (net, regex, vdpa) PMDs
to be supported at same time.
Signed-off-by: Parav Pandit <parav@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
mlx5 PCI Device supports multiple classes of devices such as net, vdpa,
and/or regex.
To support these multiple classes, change mlx5_class to a
bitmap values so that if users asks to enable multiple of them, all
supported classes can be parsed.
Signed-off-by: Parav Pandit <parav@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
mlx5_common is shared library between mlx5 net, VDPA and regex PMD.
It is better to use common initialization helper instead of using
RTE_PRIORITY_CLASS priority.
Suggested-by: David Marchand <david.marchand@redhat.com>
Signed-off-by: Parav Pandit <parav@mellanox.com>
Reviewed-by: David Marchand <david.marchand@redhat.com>
Following two errors are reported when compiled with
gcc (GCC) 8.3.1 20191121 (Red Hat 8.3.1-5).
drivers/common/mlx5/linux/mlx5_glue.h:188:2:
error: function declaration isn't a prototype [-Werror=strict-prototypes]
drivers/common/mlx5/linux/mlx5_glue.h:188:2:
error: function declaration isn't a prototype [-Werror=strict-prototypes]
Fix them by adding void data type in empty argument list.
Fixes: 34fa7c0268 ("net/mlx5: add drop action to Direct Verbs E-Switch")
Fixes: 400d985eb5 ("net/mlx5: add VLAN push/pop DR commands to glue")
Cc: stable@dpdk.org
Signed-off-by: Parav Pandit <parav@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
The mlx5 PMD did not support queue_start and queue_stop eth_dev API
routines, queue could not be suspended and resumed during device
operation.
There is the use case when this feature is crucial for applications:
- there is the secondary process handling the queue
- secondary process crashed/aborted
- some mbufs were allocated or used by secondary application
- some mbufs were allocated by Rx queues to receive packets
- some mbufs were placed to send queue
- queue goes to undefined state
In this case there was no reliable way to recovery queue handling
by restarted secondary process but reset queue to initial state
freeing all involved resources, including buffers involved in queue
operations, reset the mbuf pools, and then reinitialize queue
to working state:
- reset mbuf pool, allocate all mbuf to initialize pool into
safe state after the crush and allow safe mbuf free calls
- stop queue, free all potentially involved mbufs
- reset mbuf pool again
- start queue, reallocate mbufs needed
This patch introduces the queue start/stop feature with some
limitations:
- hairpin queues are not supported
- it is application responsibility to synchronize start/stop
with datapath routines, rx/tx_burst must be suspended during
the queue_start/queue_stop calls
- it is application responsibility to track queue usage and
provide coordinated queue_start/queue_stop calls from
secondary and primary processes.
- Rx queues with vectorized Rx routine and engaged CQE
compression are not supported by this patch currently
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Several source files include Verbs header files as in (1). These source
files will not compile under non-Linux operating systems. This commit
removes this inclusion in two cases:
Case 1: There is no usage of ibv_* or mlx5dv_* symbols in the source
file so the inclusion in (1) can be safely removed.
Case 2: Verbs symbols are used. Please note the inclusion in (1) already
appears in file linux/mlx5_glue.h (which represents the interface
to the rdma-core library). Therefore, replace (1) in the source file
with (2). Under non-Linux operating systems - file mlx5_glue.h will not
include (1).
(1)
#include <infiniband/verbs.h>
#include <infiniband/mlx5dv.h>
(2)
#include <mlx5_glue.h>
Signed-off-by: Ophir Munk <ophirmu@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
The following Linux calls are replaced by their matching rte APIs.
mmap ==> rte_mem_map()
munmap == >rte_mem_unmap()
sysconf(_SC_PAGESIZE) ==> rte_mem_page_size()
Signed-off-by: Ophir Munk <ophirmu@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
As scatter FCS might be not supported for decapsulated tunnel
packets in some NIC HW, a new capability bit which indicates
if scatter FCS works with decap is added.
Signed-off-by: Suanming Mou <suanmingm@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
This commit allocates the data path object page and B-tree table memory
from unified malloc function with explicit flag MLX5_MEM_RTE.
Signed-off-by: Suanming Mou <suanmingm@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
This commit allocates the control path objects memory from the unified
malloc function.
These objects are all used during the instances initialize, it will not
affect the data path.
Signed-off-by: Suanming Mou <suanmingm@mellanox.com>
Signed-off-by: Ali Alnubani <alialnu@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
Add the internal mlx5 memory management functions:
mlx5_malloc_mem_select();
mlx5_memory_stat_dump();
mlx5_rellaocate();
mlx5_malloc();
mlx5_free();
User will be allowed to manage memory from system or from rte memory
with the unified functions.
In this case, for the system with limited memory which can not reserve
lots of rte hugepage memory in advanced, will allocate the memory from
system for some of not so important control path objects based on the
sys_mem_en configuration.
Signed-off-by: Suanming Mou <suanmingm@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
In order to use dynamic flex parser to parse protocols that is not
supported natively, two steps are needed.
Firstly, creating the parse graph node. There are three parts of the
flex parser: node, arc and sample. Node is the whole structure of a
flex parser, when creating, the length of the protocol should be
specified. Then the input arc(s) is(are) mandatory, it will tell the
HW when to use this parser to parse the packet. For a single parser
node, up to 8 input arcs could be supported and it gives SW ability
to support this protocol over multiple layers. The output arc is
optional and also up to 8 arcs could be supported. If the protocol
is the last header of the stack, then output arc should be NULL. Or
else it should be specified. The protocol type in the arc is used to
indicate the parser pointing to or from this flex parser node. For
output arc, the next header type field offset and size should be set
in the node structure, then the HW could get the proper type of the
next header and decide which parser to point to.
Note: the parsers have two types now, native parser and flex parser.
The arc between two flex parsers are not supported in this stage.
Secondly, querying the sample IDs. If the protocol header parsed
with flex parser needs to used in flow rule offloading, the DW
samples are needed when creating the parse graph node. The offset
of bytes starting from the header needs to be set. After creating
the node successfully, a general object handle will be returned.
This object could be queried with Devx command to get the sample
IDs.
When creating a flow, sample IDs could be used to sample a DW from
the parsed header - 4 continuous bytes starting from the offset. The
flow entry could specify some mask to use part of this DW for
matching. Up to 8 samples could be supported for a single parse
graph node. The offset should not exceed the header length.
The HW resources have some limitation, low layer driver error should
be checked once there is a failure of creating parse graph node.
Signed-off-by: Netanel Gonen <netanelg@mellanox.com>
Signed-off-by: Bing Zhao <bingz@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
The structures and other definitions will be used for the dynamic
flex parser creation via Devx command interface. These structures
will be used as some some intermediate variables and input
parameters for the parser creation API.
It is better to keep all members consistent with the PRM definition
even though some of them will not be used.
Signed-off-by: Bing Zhao <bingz@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
In the translation stage, the eCPRI item should be translated into
the format that lower layer driver could use. All the fields that
need to match must be in network byte order after translation, as
well as the mask. Since the header in the item belongs to the network
layers stack, and the input parameter of the header is considered to
be in big-endian format already.
Base on the definition in the PRM, the DW samples will be used for
matching in the FTE/STE. Now, the type field and only the PC ID, RTC
ID, and DLY MSR ID of the payload will be supported. The masks should
be 00 ff 00 00 ff ff(00) 00 00 in the network order. Two DWs are
needed to support such matching. The mask fields could be zeros to
support some wildcard rules. But it makes no sense to support the
rule matching only on the payload but without matching type field.
The DW samples should be stored after the flex parser creation for
eCPRI. There is no need to query the sample IDs each time when
creating a flow rule with eCPRI item. It will not introduce
insertion rate degradation significantly.
Signed-off-by: Bing Zhao <bingz@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
The DevX routine to read/write NIC registers via DevX API is added.
This is the preparation step to check timestamp modes and units
and gather the extended statistics.
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
This patch prepares the common part of the mlx5 PMDs to
support packet send scheduling on mbuf timestamps:
- the DevX routine to query the packet pacing HCA capabilities
- packet pacing Send Queue attributes support
- the hardware related definitions
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
In case the ibverbs glue is a separate library to dlopen,
the PMD library must allocate a glue structure to be filled by dlopen.
The glue management was in mlx5_common.c and moved to mlx5_common_os.c,
but the variable allocation was not removed from the original file.
The consequence was a link failure, if ibverbs dlopen option is enabled,
because of the redefinition of the variable (with GCC 10):
multiple definition of 'mlx5_glue'
The original definition is removed to keep only the one moved
in the Linux sub-directory.
Fixes: 79aa430721 ("common/mlx5: split common file under Linux directory")
Cc: stable@dpdk.org
Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
Acked-by: Matan Azrad <matan@mellanox.com>
This commit introduce the RegEx poll mode drivers class, and
adds Mellanox RegEx PMD.
Signed-off-by: Yuval Avnery <yuvalav@mellanox.com>
Signed-off-by: Ori Kam <orika@mellanox.com>
This patch makes the Infiniband device physical port name
recognition more strict. Currently mlx5 PMD might recognize
the names like "pf0sf0" erroneously as "pf0" and the wrong
device type (host PF representor) is reported.
The names like "pf0sf0" belong to PCI subfunctions which
is currently not supported by mlx5 PMD and this false
recognition must be eliminated.
Fixes: 420bbdae89 ("net/mlx5: fix host physical function representor naming")
Cc: stable@dpdk.org
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
This adds the ConnectX-6 Lx device id to the list of supported
Mellanox devices that run the MLX5 PMD.
The device is still in development stage.
Signed-off-by: Ali Alnubani <alialnu@mellanox.com>
Acked-by: Raslan Darawsheh <rasland@mellanox.com>
Enable/disable link state interrupt and get link state api is
defined using IOCTL calls from kernel driver
Signed-off-by: Rohit Raj <rohit.raj@nxp.com>
Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>
Interrupt callback unregister can fail with -EAGAIN
when interrupt handler is active in interrupt thread.
Hence retry before reporting a failure or proceeding further.
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Segmentation fault has been observed while running procinfo
with reset options i.e. --stats-reset and --xstats-reset.
Reason is procinfo runs as a secondary process and tries to
hold a lock which is part of struct mdev, which was not
allocated as part of shared memory.
Fixes: 5ca59711f7 ("common/octeontx2: add mailbox base support infra")
Cc: stable@dpdk.org
Signed-off-by: Harman Kalra <hkalra@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
As cryptodev driver_id is allocated per-process,
a corner case exists where binaries for primary and
secondary processes could have different driver_ids
if built differently. Add checking in qat PMD to catch and
handle the case where driver_ids are inconsistent.
Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>
This patch refactors qat data into structures
which are local to the process and structures which
are intended to be shared by primary and secondary
processes. This enables qat devices to be used by
multi process applications.
Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>
In case of LX2160, PROTOCOL command can be used in some of the PDCP
cases, in those the jump command prior to KEY command may not be
required.
The issue observed due to these JUMP command on LX2160 is that,
the CAAM gets stuck and the processing never get completed. The
system becomes unusable.
Signed-off-by: Akhil Goyal <akhil.goyal@nxp.com>
Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>
In cases of NULL auth in PDCP, the descriptors
should be based on ALGORITHM command instead of
PROTOCOL command.
It was done in case of encap, but was missing in
decap.
Fixes: 526cdf60f1 ("crypto/dpaa2_sec: update desc for PDCP 18-bit enc-auth")
Cc: stable@dpdk.org
Signed-off-by: Akhil Goyal <akhil.goyal@nxp.com>
Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>
The maximum length of job descriptor which is formed
is 13 words and hence rta_inline_query should take
care of the max descriptor(shared + job) lengths and
thus find out of the key can be referenced or immediate.
Fixes: 05b12700cd ("crypto/dpaa_sec: support null algos for protocol offload")
Fixes: 13273250ee ("crypto/dpaa2_sec: support AES-GCM and CTR")
Cc: stable@dpdk.org
Signed-off-by: Akhil Goyal <akhil.goyal@nxp.com>
Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>
In case of RTA_SEC_ERA = 8, where the length of shared desc
is large for some of PDCP cases, the descriptor buffer cannot
hold 2 extra words when HFN override is enabled. As a result,
the descriptor fails.
This patch converts one of the keys from immediate key to
reference key hence reducing the length of the descriptor.
Fixes: 2e4cbdb4b2 ("crypto/dpaax_sec: support PDCP U-Plane with integrity")
Cc: stable@dpdk.org
Signed-off-by: Akhil Goyal <akhil.goyal@nxp.com>
Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>
Populate capabilities based on device features.
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
In case of gmac auth the encryption offset should be set to zero.
Fixes: b74652f3a9 ("common/cpt: add microcode interface for encryption")
Fixes: 177b41ceee ("common/cpt: add microcode interface for decryption")
Cc: stable@dpdk.org
Signed-off-by: Ankur Dwivedi <adwivedi@marvell.com>
Add support to the QAT SYM PMD for the DOCSIS protocol, through the
rte_security API. This, therefore, includes adding support for the
rte_security API to this PMD.
Signed-off-by: David Coyle <david.coyle@intel.com>
Signed-off-by: Mairtin o Loingsigh <mairtin.oloingsigh@intel.com>
Now that all libraries have a single version, we can drop the empty
stable blocks that had been added when moving symbols from stable to
internal ABI.
Signed-off-by: David Marchand <david.marchand@redhat.com>
Acked-by: Bruce Richardson <bruce.richardson@intel.com>
Introduce the RTE_LOG_REGISTER macro to avoid the code duplication
in the logtype registration process.
It is a wrapper macro for declaring the logtype, registering it and
setting its level in the constructor context.
Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Acked-by: Adam Dybkowski <adamx.dybkowski@intel.com>
Acked-by: Sachin Saxena <sachin.saxena@nxp.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
Some compilers raise an error when declaring a variable
in the middle of a function. This is a C99 allowance.
Even if DPDK switches globally to C99 or C11 standard,
the coding rules are for declarations at the beginning
of a block:
http://doc.dpdk.org/guides/contributing/coding_style.html#local-variables
This coding style is enforced by adding a check of
the common patterns like "for (int i;"
The occurrences of the checked pattern are fixed:
'for *(\(char\|u\?int\|unsigned\|s\?size_t\)'
In the file dpaa2_sparser.c, the fix is to remove the unused macros.
Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
Acked-by: David Marchand <david.marchand@redhat.com>
allow_experimental_apis flag has no effect for in-tree compilation.
See https://git.dpdk.org/dpdk/commit/?id=acec04c4b2f5
Fixes: 72f7566056 ("common/mlx5: move glue files under Linux directory")
Signed-off-by: David Marchand <david.marchand@redhat.com>
Acked-by: Raslan Darawsheh <rasland@mellanox.com>
The mlx5_dev_to_pci_addr function defines a variable called ret inside a
loop and uses it.
During the loop, the function assigns a value within the variable and
breaks from the loop, so that this assigning has done nothing and is
actually unnecessary.
Remove the unnecessary assigning.
Signed-off-by: Michael Baum <michaelba@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
Flow tag action is supported only when the driver has DR or DV support.
The tag allocation is adjusted to the modes DV or DR.
In case both DR and DV are not supported in the system, the driver
handles static code for error report.
This error code, wrongly, was compiled when DV is supported while in
this case it cannot be accessed at all.
Ignore the aforementioned static error code in case of DV by
preprocessor commands rearrangement.
Fixes: cbb66daa3c ("net/mlx5: prepare Direct Verbs for Direct Rule")
Cc: stable@dpdk.org
Signed-off-by: Michael Baum <michaelba@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
Add dv_create_action_default_miss wrapper function
for the action added to the rdma-core
MLX5DV_FLOW_ACTION_DEFAULT_MISS.
When a packet matches MLX5DV_FLOW_ACTION_DEFAULT_MISS
action it is steered to the default miss of the verbs
steering domain.
Signed-off-by: Shiri Kuzin <shirik@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
New cn98xx SOC comes up with two NIX blocks wrt
cn96xx, cn93xx, to achieve higher performance.
Also the no of cores increased to 36 from 24.
Adding support for cn98xx where need a logic to
detect if the LF is attached to NIX0 or NIX1 and
then accordingly use the respective NIX block.
Signed-off-by: Harman Kalra <hkalra@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
The new kernel adds the names like "pf0" for Host PCI physical
function representor on Bluefield SmartNIC hosts. This patch
provides correct HPF representor recognition over the kernel
versions 5.7 and laters.
The following port naming formats are supported:
- missing physical port name (no sysfs/netlink key) at all,
master is assumed
- decimal digits (for example "12"), representor is
assumed, the value is the index of attached VF
- "p" followed by decimal digits, for example "p2", master
is assumed
- "pf" followed by PF index, for example "pf0", Host PF
representor is assumed on SmartNIC systems.
- "pf" followed by PF index concatenated with "vf" followed by
VF index, for example "pf0vf1", representor is assumed.
If index of VF is "-1" it is a special case of Host PF
representor, this representor must be indexed in devargs
as 65535, for example representor=[0-3,65535] will
allow representors for VF0, VF1, VF2, VF3 and for host PF.
Fixes: 79aa430721 ("common/mlx5: split common file under Linux directory")
Cc: stable@dpdk.org
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
The creation of DBR can be used by a number of different
Mellanox PMDs. for example RegEx / Net / VDPA.
This commits moves the DBR creation and release functions to common
folder.
Signed-off-by: Ori Kam <orika@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Getter functions such as: 'mlx5_os_get_ctx_device_name',
'mlx5_os_get_ctx_device_path', 'mlx5_os_get_dev_device_name',
'mlx5_os_get_umem_id' are implemented under net directory. To enable
additional devices (e.g. regex, vdpa) to access these getter functions
they are moved under common directory.
As part of this commit string sizes DEV_SYSFS_NAME_MAX and
DEV_SYSFS_PATH_MAX are increased by 1 to make sure that the destination
string size in strncpy() function is bigger than the source string size.
This update will avoid GCC version 8 error -Werror=stringop-truncation.
Signed-off-by: Ophir Munk <ophirmu@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
Some configuration of the mlx5 port are done by the kernel net device
associated to the IB device represents the PCI device.
The DPDK mlx5 driver uses Linux system calls, for example ioctl, in
order to configure per port configurations requested by the DPDK user.
One of the basic knowledges required to access the correct kernel net
device is its name.
Move function to get interface name from IB device path to the common
library.
Signed-off-by: Matan Azrad <matan@mellanox.com>
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
Starting from FW version 22.27.4002, it is required to
configure protection domain (PD) for each virtq created by
DevX.
Add PD requirement in virtq DevX APIs.
Cc: stable@dpdk.org
Signed-off-by: Matan Azrad <matan@mellanox.com>
Signed-off-by: Xueming Li <xuemingl@mellanox.com>
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
Add DevX API to create and query virtio queue statistics
from the HW. The next counters are supported by the HW per
virtio queue:
received_desc.
completed_desc.
error_cqes.
bad_desc_errors.
exceed_max_chain.
invalid_buffer.
Signed-off-by: Matan Azrad <matan@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
Prior to this commit MR operations were verbs based and hard coded under
common/mlx5/linux directory. This commit enables upper layers (e.g.
net/mlx5) to determine which MR operations to use. For example the net
layer could set devx based MR operations in non-Linux environments. The
reg_mr and dereg_mr callbacks are added to the global per-device MR
cache 'struct mlx5_mr_share_cache'.
Signed-off-by: Ophir Munk <ophirmu@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
The glue verbs operations reg_mr and dereg_mr are wrapped and exported
in functions mlx5_common_verbs_reg_mr and mlx5_common_verbs_dereg_mr
respectively. The exported functions are added to a new file
linux/mlx5_common_verbs.c.
Signed-off-by: Ophir Munk <ophirmu@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
Replace 'struct ibv_mr *' (in 'struct mlx5_mr') with a new 'struct
mlx5_pmd_mr'. The new struct contains the required MR field: lkey,
addr, len and is independent of ibv.
Signed-off-by: Ophir Munk <ophirmu@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
Function mlx5_devx_cmd_qp_query_tis_td() receives as parameter a pointer
to verbs QP returned by ibv_create_qp. Therefore support it only if
HAVE_IBV_FLOW_DV_SUPPORT is defined. Otherwise return an error ENOTSUP.
Signed-off-by: Ophir Munk <ophirmu@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
Replace 'struct ibv_pd *' with 'void *' in struct mlx5_ctx_shared and
all function calls in mlx5 PMD.
Signed-off-by: Ophir Munk <ophirmu@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
While flow destroyed, rdma-core may still cache some resources for more
efficiently flow recreate. In case the peak time that millions of flows
created and destroyed, the cached resources will be very huge.
Currently, rdma-core provides the new function to configure the flow
resources not to be cached. Add the memory reclaim function to avoid
too many resources be cached.
This is the first patch for the memory reclaim. A new devarg will be
added to PMD to support the reclaim can be configured.
Signed-off-by: Suanming Mou <suanmingm@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
File mlx5_common.c includes both specific and non-specific Linux APIs.
Move the Linux specific APIS into a new file named linux/mlx5_common_os.c.
Signed-off-by: Ophir Munk <ophirmu@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
File mlx5_nl.c is using Netlink APIs which are Linux specifics.
Move it (including file mlx5_nl.h) to common/mlx5/linux directory.
Signed-off-by: Ophir Munk <ophirmu@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
The glue file mlx5_glue.c is based on Linux specifics APIs.
Move it (including file mlx5_glue.h) to common/mlx5/linux directory.
Signed-off-by: Ophir Munk <ophirmu@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
Add device arguments to lock NPA aura and pool contexts in NDC cache.
The device args take hexadecimal bitmask where each bit represent the
corresponding aura/pool id.
Example:
-w 0002:02:00.0,npa_lock_mask=0xf // Lock first 4 aura/pool ctx
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
This patch moves the internal symbols to INTERNAL sections
so that any change in them is not reported as ABI breakage.
Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
Acked-by: Ray Kinsella <mdr@ashroe.eu>
Clarify Intel copyright and update the date to 2020.
Fixes: 317862a4e4 ("net/iavf: replace license text with SPDX tag")
Cc: stable@dpdk.org
Signed-off-by: Xiaoyun Li <xiaoyun.li@intel.com>
Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
The buffer size to receive netlink reply messages is relatively
large (32K), and it is allocated on the stack and it might
break in application is using smaller per-thread stacks.
This patch allocates temporary buffer from heap.
Fixes: ccdcba53a3 ("net/mlx5: use Netlink to add/remove MAC addresses")
Cc: stable@dpdk.org
Reported-by: Stephen Hemminger <stephen@networkplumber.org>
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
The MLX5 device supports up to MLX5_MAX_MAC_ADDRESSES (256) MAC
addresses. The code flushes all MAC devices.
If DPDK is compiled with MLX5_DEBUG this would an assert.
PANIC in mlx5_nl_mac_addr_flush():
line 775 assert "(size_t)(i) < sizeof(mac_own) * 8" failed
The root cause is that mac_own is a pointer and is being used as
a bitmap array. The sizeof(mac_own) would therefore be 64 but the
number of entries to be flushed would be 256.
There is a whole set of asserts in MLX5 netlink code with
the same bug; that should just be changed into proper error checks.
Fixes: 8e46d4e18f ("common/mlx5: improve assert control")
Cc: stable@dpdk.org
Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
A typo need to be fixed for Simple XOR algorithm configuration.
Fixes: 57094d5943 ("common/iavf: support advanced RSS input set change")
Signed-off-by: Jeff Guo <jia.guo@intel.com>
Acked-by: Xiaolong Ye <xiaolong.ye@intel.com>
Relaxed ordering is a PCI optimization that enables reordering
reads/writes in order to improve performance.
Relaxed ordering was enabled for all processors causing
a degradation in performance in Haswell and Broadwell processors
that don't support this optimization.
In order to avoid that we check if the processor is Haswell
or Broadwell and if so we disable relaxed ordering.
Signed-off-by: Shiri Kuzin <shirik@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
In order to improve performance relaxed ordering was enabled
when creating count object using Devx.
Currently rte enables this optimization by default when using
Devx.
This causes an issue when using firmware that does not have this
capability causing a count object failure.
In order to fix this issue a check of firmware capabilities was
added before enabling relaxed ordering.
Fixes: 53ac93f71a ("net/mlx5: create relaxed ordering memory regions")
Signed-off-by: Shiri Kuzin <shirik@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
Relaxed ordering is a PCI optimization that allows reordering
of reads/writes in order to improve performance.
In order to enable this optimization only when relaxed ordering
is supported, it is checked if IBV_ACCESS_RELAXED_ORDERING is
defined in verbs.h.
Since IBV_ACCESS_RELAXED_ORDERING is an enum and not
defined relaxed ordering wasn't enabled even when supported.
This issue is fixed by using AUTOCONF to check if relaxed
ordering is supported and disabling only if it isn't.
Fixes: 53ac93f71a ("net/mlx5: create relaxed ordering memory regions")
Signed-off-by: Shiri Kuzin <shirik@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
The value MLX5_WQE_BUF_ALIGNMENT is defined as 512.
In some cases this alignment size is not adequate, which results in
memory registration that is not accepted by FW.
The result error can be "page_offset is not aligned to page_size/64,
bad umem_offset" (syndrome 0x357275).
This patch updates the definition to match the running system.
Fixes: 18a68e046b ("net/mlx5: fix DevX Rx queue memory alignment")
Cc: stable@dpdk.org
Signed-off-by: Dekel Peled <dekelp@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
File mlx5_devx_cmds.c should contain pure DevX calls. It must be OS
agnostic and not include any references to ibv or dv structs (defined in
ibverbs and rdma-core linux libraries). This commit replaces all ibv
and dv references with 'void *'. Specifically, the following struct
were replaced:
1. struct ibv_context *
2. struct ibv_qp *
3. struct mlx5dv_devx_cmd_comp *
Signed-off-by: Ophir Munk <ophirmu@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
Move mlx5 symbols in the map file to the INTERNAL section and add
__internal tags to their definitions.
Those symbols were exported in 20.02 and now (20.05) they are removed.
Avoid ABI comparison issues between 20.05/20.08 and 20.02 by adding the
suppress_file directive to libabigail.abignore file. This directive will
prevent loading mlx5 common symbols and no comparison will be performed.
In addition move symbols from the EXPERIMENTAL section to the INTERNAL
section.
Fixes: 7b4f1e6bd3 ("common/mlx5: introduce common library")
Signed-off-by: Ophir Munk <ophirmu@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
Move the internal symbols to INTERNAL sections so that any
change in them is not reported as ABI breakage.
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Acked-by: Ray Kinsella <mdr@ashroe.eu>
Signed-off-by: David Marchand <david.marchand@redhat.com>
gcc 10 defaults to -fno-common and as a result when linking
with crypto drivers:
drivers/librte_pmd_dpaa_sec.a(crypto_dpaa_sec_dpaa_sec.c.o):
(.bss+0x4): multiple definition of `rta_sec_era';
drivers/librte_pmd_caam_jr.a(crypto_caam_jr_caam_jr.c.o):
(.bss+0x0): first defined here
drivers/librte_pmd_dpaa2_sec.a(crypto_dpaa2_sec_dpaa2_sec_dpseci.c.o):
(.data+0x0): multiple definition of `rta_sec_era';
drivers/librte_pmd_caam_jr.a(crypto_caam_jr_caam_jr.c.o):
(.bss+0x0): first defined here
This patch fixes the blunt workaround in the following commit.
Fixes: 50b03f3b8e ("drivers/crypto: disable gcc 10 no-common errors")
Bugzilla ID: 469
Cc: stable@dpdk.org
Signed-off-by: Akhil Goyal <akhil.goyal@nxp.com>
Tested-by: Kevin Traynor <ktraynor@redhat.com>
Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>
Acked-by: Ray Kinsella <mdr@ashroe.eu>
This patch removed the non-essential check for NULL pointer.
Coverity issue: 357770
Fixes: c13cecf60f ("compress/qat: support IM buffer too small operation")
Signed-off-by: Adam Dybkowski <adamx.dybkowski@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>
This patch fixes enqueued and dequeued count statistics that should
contain the number of operations enqueued by the end user app
instead of the total number of QAT requests - bigger in case of
a multiple-request dynamic Huffman compression operation.
Fixes: c13cecf60f ("compress/qat: support IM buffer too small operation")
Signed-off-by: Adam Dybkowski <adamx.dybkowski@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>
This patch fixes missing queue head update that occurred when
a multiple-request dynamic Huffman compression operation was not
complete within one qat_dequeue_op_burst function call.
Fixes: c13cecf60f ("compress/qat: support IM buffer too small operation")
Signed-off-by: Adam Dybkowski <adamx.dybkowski@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>
Tested-by: Xinfeng Zhao <xinfengx.zhao@intel.com>
GCC 9.1 fixes a bug with passing bitfields as pass by value in function
parameters and generates a warning for the same as below:
drivers/common/octeontx/octeontx_mbox.c:282:1: note: parameter passing
for argument of type ‘struct mbox_intf_ver’ changed in GCC 9.1
Fix the warning generated by passing bitfield as pass by reference.
Fixes: b4134b2d31 ("common/octeontx: update mbox to version 1.1.3")
Cc: stable@dpdk.org
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Acked-by: Harman Kalra <hkalra@marvell.com>
Tested-by: Ferruh Yigit <ferruh.yigit@intel.com>
Gcc 8.3.0 (Debian 10) complains about uninitialized variable.
[474/2122] Compiling C object
'drivers/a715181@@tmp_rte_common_mlx5@sta/common_mlx5_mlx5_nl.c.o'.
In file included from ../drivers/common/mlx5/mlx5_nl.h:12,
from ../drivers/common/mlx5/mlx5_nl.c:23:
../drivers/common/mlx5/mlx5_nl.c: In function ‘mlx5_nl_enable_roce_get’:
../drivers/common/mlx5/mlx5_common.h:68:2: warning: ‘cur_en’ may be used
uninitialized in this function [-Wmaybe-uninitialized]
rte_log(RTE_LOG_ ## level, \
^~~~~~~
../drivers/common/mlx5/mlx5_nl.c:1560:6: note: ‘cur_en’ was declared here
int cur_en;
^~~~~~
The compiler is correct, this variable would only be set if kernel
netlink response message contains the DEVLINK parameter that flags if
ROCE is enabled.
Fixes: fa69eaef5f ("common/mlx5: support ROCE disable through Netlink")
Cc: stable@dpdk.org
Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
The AltiVec header file breaks boolean type. [1] [2]
Currently the workaround was located only in mlx5 device.
Adding the trace module caused this issue to appear again, due to
order of includes, it keeps overriding the local fix.
This patch solves this issue by resetting the bool type, immediately
after it is being changed.
[1] https://mails.dpdk.org/archives/dev/2018-August/110281.html
[2]
In file included from
dpdk/ppc_64-power8-linux-gcc/include/rte_mempool_trace_fp.h:18:0,
from
dpdk/ppc_64-power8-linux-gcc/include/rte_mempool.h:54,
from
dpdk/drivers/common/mlx5/mlx5_common_mr.c:7:
dpdk/ppc_64-power8-linux-gcc/include/rte_trace_point.h: In
function '__rte_trace_point_fp_is_enabled':
dpdk/ppc_64-power8-linux-gcc/include/rte_trace_point.h:226:2:
error: incompatible types when returning type 'int' but '__vector __bool
int' was expected
return false;
^
In file included from
dpdk/ppc_64-power8-linux-gcc/include/rte_trace_point.h:281:0,
from
dpdk/ppc_64-power8-linux-gcc/include/rte_mempool_trace_fp.h:18,
from
dpdk/ppc_64-power8-linux-gcc/include/rte_mempool.h:54,
from
dpdk/drivers/common/mlx5/mlx5_common_mr.c:7:
dpdk/ppc_64-power8-linux-gcc/include/rte_mempool_trace_fp.h:
In function 'rte_mempool_trace_ops_dequeue_bulk':
dpdk/ppc_64-power8-linux-gcc/include/rte_trace_point_provider.h:104:6:
error: wrong type argument to unary exclamation mark
if (!__rte_trace_point_fp_is_enabled()) \
^
dpdk/ppc_64-power8-linux-gcc/include/rte_trace_point.h:49:2:
note: in expansion of macro '__rte_trace_point_emit_header_fp'
__rte_trace_point_emit_header_##_mode(&__##_tp); \
^
dpdk/ppc_64-power8-linux-gcc/include/rte_trace_point.h:99:2:
note: in expansion of macro '__RTE_TRACE_POINT'
__RTE_TRACE_POINT(fp, tp, args, __VA_ARGS__)
^
dpdk/ppc_64-power8-linux-gcc/include/rte_mempool_trace_fp.h:20:1:
note: in expansion of macro 'RTE_TRACE_POINT_FP'
RTE_TRACE_POINT_FP(
^
dpdk/ppc_64-power8-linux-gcc/include/rte_mempool_trace_fp.h:
In function 'rte_mempool_trace_ops_dequeue_contig_blocks':
dpdk/ppc_64-power8-linux-gcc/include/rte_trace_point_provider.h:104:6:
error: wrong type argument to unary exclamation mark
if (!__rte_trace_point_fp_is_enabled()) \
^
dpdk/ppc_64-power8-linux-gcc/include/rte_trace_point.h:49:2:
note: in expansion of macro '__rte_trace_point_emit_header_fp'
__rte_trace_point_emit_header_##_mode(&__##_tp); \
^
dpdk/ppc_64-power8-linux-gcc/include/rte_trace_point.h:99:2:
note: in expansion of macro '__RTE_TRACE_POINT'
__RTE_TRACE_POINT(fp, tp, args, __VA_ARGS__)
^
dpdk/ppc_64-power8-linux-gcc/include/rte_mempool_trace_fp.h:29:1:
note: in expansion of macro 'RTE_TRACE_POINT_FP'
RTE_TRACE_POINT_FP(
^
dpdk/ppc_64-power8-linux-gcc/include/rte_mempool_trace_fp.h:
In function 'rte_mempool_trace_ops_enqueue_bulk':
dpdk/ppc_64-power8-linux-gcc/include/rte_trace_point_provider.h:104:6:
error: wrong type argument to unary exclamation mark
if (!__rte_trace_point_fp_is_enabled()) \
Fixes: 725f5dd0bf ("net/mlx5: fix build on PPC64")
Signed-off-by: Ori Kam <orika@mellanox.com>
Signed-off-by: David Christensen <drc@linux.vnet.ibm.com>
Tested-by: David Christensen <drc@linux.vnet.ibm.com>
Tested-by: Raslan Darawsheh <rasland@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
Change references to ABI 20.0.1 to use ABI v21, see
https://doc.dpdk.org/guides/contributing/abi_policy.html#general-guidelines
"Major ABI versions are declared no more frequently than yearly.
Compatibility with the major ABI version is mandatory in subsequent
releases until a new major ABI version is declared."
Combined ABI policy and versioning in maintainers, add map files to the
filter to more closely monitor future ABI changes.
Signed-off-by: Ray Kinsella <mdr@ashroe.eu>
drivers/common/mlx5/mlx5_glue.c: In function 'mlx5_glue_devx_qp_query':
drivers/common/mlx5/mlx5_glue.c:1010:9: error:
implicit declaration of function 'mlx5dv_devx_qp_query'
The function mlx5dv_devx_qp_query() was added in rdma-core 22.
This function is compiled only if HAVE_IBV_DEVX_OBJ,
which is true if the function mlx5dv_devx_obj_create is found.
Unfortunately mlx5dv_devx_obj_create() was introduced in rdma-core 21,
when mlx5dv_devx_qp_query() did not exist yet.
A new flag HAVE_IBV_DEVX_QP is added when mlx5dv_devx_qp_query()
is found.
Fixes: 62d6f70f30 ("net/mlx5: add glue for queue query via DevX")
Cc: stable@dpdk.org
Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Refactor common memory btree and cache management to common driver.
Replace some input parameters of MR APIs to more common data structure
like PD, port_id, share_cache,... so that multiple PMD drivers can
use those MR APIs.
Modify mlx5 net pmd driver to use MR management APIs from common driver.
Signed-off-by: Vu Pham <vuhuong@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Refactor common multi-process handling codes from net PMD to common
driver. Using tuple mp_id{name, port_id} as standard input parameter
for all multi-process IPC APIs instead of using rte_eth_dev.
Modify net PMD to use multi-process APIs from common driver.
Signed-off-by: Vu Pham <vuhuong@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
The variable storages of the same name are merged together
if compiled with -fcommon. This is the default.
This default behaviour allows to declare a variable in a header file and
share the variable in every .o binaries thanks to merge at link-time.
In the case of dlopen linking of the glue library, the pointer mlx5_glue
is referencing the glue functions struct and is set after calling
dlopen.
If compiling with -fno-common (default in GCC 10), the variable must be
declared as extern to avoid multiple re-definitions.
In case the glue layer is split in glue library, the variable mlx5_glue
needs to have its own storage for the rest of the PMD.
Cc: stable@dpdk.org
Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
Acked-by: Matan Azrad <matan@mellanox.com>
The function mlx5_glue_init was doing three things:
- initialize logs
- load glue library if in dlopen mode
- initialize glue layer
They are split in three functions for clarity.
The config option RTE_IBVERBS_LINK_DLOPEN is not used anymore
outside of make and meson files. It is replaced with MLX5_GLUE,
which is defined in the same condition and is already used with dlopen.
Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
Acked-by: Matan Azrad <matan@mellanox.com>
Adds new ops and structures to support VF to add/delete/validate/
query flow director.
ADD and VALIDATE FDIR share one ops: VIRTCHNL_OP_ADD_FDIR_FILTER.
VF sends this request to PF by filling out the related field in
virtchnl_fdir_add. If the rule is created successfully, PF
will return flow id and program status to VF. If the rule is
validated successfully, the PF will only return program status
to VF.
DELETE FDIR uses ops: VIRTCHNL_OP_DEL_FDIR_FILTER.
VF sends this request to PF by filling out the related field in
virtchnl_fdir_del. If the rule is deleted successfully, PF
will return program status to VF.
Query FDIR uses ops: VIRTCHNL_OP_QUERY_FDIR_FILTER.
VF sends this request to PF by filling out the related field in
virtchnl_fdir_query. If the request is successfully done by PF,
PF will return program status and query info to VF.
Signed-off-by: Simei Su <simei.su@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Beilei Xing <beilei.xing@intel.com>
Add new ops and a new VIRTCHNL_VF_OFFLOAD_ADV_RSS_PF flag to support
VF to add or del a specific rss configuration by virtchnl.
Signed-off-by: Jeff Guo <jia.guo@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Beilei Xing <beilei.xing@intel.com>
To support advanced AVF's FDIR and RSS feature, we need to figure out
what kind of data structure should be passed from VF to PF to describe
an FDIR rule or RSS config rule. The common part of the requirement is
we need a data structure to represent the input set selection of a rule's
hash key.
An input set selection is a group of fields be selected from one or more
network protocol layers that could be identified as a specific flow.
For example, select dst IP address from an IPv4 header combined with
dst port from the TCP header as the input set for an IPv4/TCP flow.
The patch adds a new data structure virtchnl_proto_hdrs to abstract
a network protocol headers group which is composed of layers of network
protocol header(virtchnl_proto_hdr).
A protocol header contains a 32 bits mask (field_selector) to describe
which fields are selected as input sets, as well as a header type
(enum virtchnl_proto_hdr_type). Each bit is mapped to a field in
enum virtchnl_proto_hdr_field guided by its header type.
+------------+-----------+------------------------------+
| | Proto Hdr | Header Type A |
| | +------------------------------+
| | | BIT 31 | ... | BIT 1 | BIT 0 |
| |-----------+------------------------------+
|Proto Hdrs | Proto Hdr | Header Type B |
| | +------------------------------+
| | | BIT 31 | ... | BIT 1 | BIT 0 |
| |-----------+------------------------------+
| | Proto Hdr | Header Type C |
| | +------------------------------+
| | | BIT 31 | ... | BIT 1 | BIT 0 |
| |-----------+------------------------------+
| | .... |
+-------------------------------------------------------+
All fields in enum virtchnl_proto_hdr_fields are grouped with header type
and the value of the first field of a header type is always 32 aligned.
enum proto_hdr_type {
header_type_A = 0;
header_type_B = 1;
....
}
enum proto_hdr_field {
/* header type A */
header_A_field_0 = 0,
header_A_field_1 = 1,
header_A_field_2 = 2,
header_A_field_3 = 3,
/* header type B */
header_B_field_0 = 32, // = header_type_B << 5
header_B_field_0 = 33,
header_B_field_0 = 34
header_B_field_0 = 35,
....
};
So we have:
proto_hdr_type = proto_hdr_field / 32
bit offset = proto_hdr_field % 32
To simply the protocol header's operations, couple help macros are added.
For example, to select src IP and dst port as input set for an IPv4/UDP
flow.
we have:
struct virtchnl_proto_hdr hdr[2];
VIRTCHNL_SET_PROTO_HDR_TYPE(&hdr[0], IPV4)
VIRTCHNL_ADD_PROTO_HDR_FIELD(&hdr[0], IPV4, SRC)
VIRTCHNL_SET_PROTO_HDR_TYPE(&hdr[1], UDP)
VIRTCHNL_ADD_PROTO_HDR_FIELD(&hdr[1], UDP, DST)
A protocol header also contains a byte array, this field should only
be used by an FDIR rule and should be ignored by RSS. For an FDIR rule,
the byte array is used to store the protocol header of a training
package. The byte array must be network order.
Signed-off-by: Jeff Guo <jia.guo@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Beilei Xing <beilei.xing@intel.com>
Add new VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC flag, opcode
VIRTCHNL_OP_GET_SUPPORTED_RXDIDS and add member rxdid
in struct virtchnl_rxq_info to support AVF Flex RXD
extension.
Signed-off-by: Leyi Rong <leyi.rong@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Beilei Xing <beilei.xing@intel.com>
Add VIRTCHNL_OP_DCF_GET_PKG_INFO to query DDP package identification.
Signed-off-by: Leyi Rong <leyi.rong@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Beilei Xing <beilei.xing@intel.com>
Add IAVF_RX_PTYPE_PARSER_ABORTED definition, so iavf driver will know
opcode for parser aborted packets.
Without this definition driver would have to rely on magic numbers.
Signed-off-by: Przemyslaw Patynowski <przemyslawx.patynowski@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Beilei Xing <beilei.xing@intel.com>
This commit is a part for the DV counter optimization.
The batch counter dcs id starts from 0x800000 and none batch counter
starts from 0. As currently, the counter is changed to be indexed by
pool index and the offset of the counter in the pool counters_raw array.
It means now the counter index is same for batch and none batch counter.
Add the 0x800000 batch counter offset to the batch counter index helps
indicate the counter index is from batch or none batch container pool.
Signed-off-by: Suanming Mou <suanmingm@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
This patch adds SDP packet parsing support with custom L2 header,
adds support to include a field from custom header for flow tag
generation.
Signed-off-by: Satheesh Paul <psatheesh@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Modify resource allocation and freeing logic to support
dynamic topology commit while to traffic is flowing.
This patch also modifies SQ flush to timeout based on minimum shaper
rate configured. SQ flush is further split to pre/post
functions to adhere to HW spec of 96XX C0.
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Signed-off-by: Krzysztof Kanas <kkanas@marvell.com>
Sync mail box data structures to version 0x0005 to
that of kernel AF driver.
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
In function mlx5_devx_cmd_create_tir(), the 40 bytes of RSS key are
copied in 10 iterations, 4 bytes each time using the MLX5_SET macro.
As result the RSS key is copied into TIR context in swapped byte order.
This patch fixes the issue, using memcpy() to copy the RSS key as is.
The struct member mlx5_devx_tir_attr.rx_hash_toeplitz_key is updated
to byte array type.
Fixes: c3aea272ee ("net/mlx5: create advanced Rx object via DevX")
Cc: stable@dpdk.org
Signed-off-by: Dekel Peled <dekelp@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
In the current state, when preforming read/write
transactions we must wait for a completion in order
to run the next transaction, and all transactions are
performed by order.
Relaxed Ordering is a PCI optimization which by enabling it
we allow the system to perform read/writes in a different
order without having to wait for completion and improve
the performance in that matter.
This commit introduces the creation of relaxed ordering
memory regions in mlx5.
As relaxed ordering is an optimization, drivers that
do not support it can simply ignore it and therefore
it is enabled by default.
Signed-off-by: Shiri Kuzin <shirik@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
Introduce the DCF (Device Config Function) feature in the ice PMD, it
works as a standalone PMD which doesn't handle the packet Rx/Tx related
things. Its hardware entity is the VF.
Add the basic DCF hardware initialization, this is specified by devarg
'cap=dcf'.
Signed-off-by: Haiyue Wang <haiyue.wang@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
Add an opcode for getting VSI mapping table.
Add an virtchnl event code for VF reset done.
Signed-off-by: Beilei Xing <beilei.xing@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Beilei Xing <beilei.xing@intel.com>
Add DCF capability flag for VF.
Add an opcode for disabling DCF capability.
Add an virtchnl event code for AVF resetting completion.
Signed-off-by: Xiaoyun Li <xiaoyun.li@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Beilei Xing <beilei.xing@intel.com>
Add two virtchnl opcodes to send the AdminQ command, one is used to
send the descriptor, the other is used to send the buffer payload if
the AdminQ command has BUF flag set.
Signed-off-by: Haiyue Wang <haiyue.wang@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Beilei Xing <beilei.xing@intel.com>
Update copyright date to 2020.
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Beilei Xing <beilei.xing@intel.com>
This patch implements a special way of buffer handling when internal
QAT IM buffer is too small for Huffman dynamic compression operation.
Instead of falling back to fixed compression, the operation is now
split into multiple smaller dynamic compression requests (possible to
execute on QAT) and their results are then combined and copied into
the output buffer. This is not possible if any checksum calculation
was requested - in such case the code falls back to fixed compression
as before.
Signed-off-by: Adam Dybkowski <adamx.dybkowski@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>
There is a common macro __rte_unused, avoiding warnings,
which is now used where appropriate for consistency.
Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
There is a macro __rte_noinline, preventing function to be inlined,
which is now used where appropriate for consistency.
Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
There is a common macro __rte_packed for packing structs,
which is now used where appropriate for consistency.
Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
There is a common macro __rte_aligned for alignment,
which is now used where appropriate for consistency.
Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
Reviewed-by: David Christensen <drc@linux.vnet.ibm.com>
The keyword alignas can be replaced with __rte_aligned macro
for consistency and allow compilers compatibility control.
The macro __rte_cache_aligned is a shortcut including __rte_aligned
and RTE_CACHE_LINE_SIZE constant.
Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
Remove setting ALLOW_EXPERIMENTAL_API individually for each Makefile and
meson.build. Instead, enable ALLOW_EXPERIMENTAL_API flag across app, lib
and drivers.
This changes reduces the clutter across the project while still
maintaining the functionality of ALLOW_EXPERIMENTAL_API i.e. warning
external applications about experimental API usage.
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>
Signed-off-by: David Marchand <david.marchand@redhat.com>
This patch adds the function for retrieving QAT firmware
version, required to check the internal capabilities that
depend on the FW version.
Signed-off-by: Adam Dybkowski <adamx.dybkowski@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>
The EAL API (with doxygen documentation) is moved from
common/include/ to include/, which makes more clear that
it is the global API for all environments and architectures.
Note that the arch-specific and OS-specific include files are not
in this global include directory, but include/generic/ should
cover the doxygen documentation for them.
Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
Acked-by: David Marchand <david.marchand@redhat.com>
This is a helper function in case components would like to do more work
than just logging a message based on log level, like for example
collecting some stats if the log type is DEBUG etc..
A few existing relevant usage converted to this new API.
Signed-off-by: Ferruh Yigit <ferruh.yigit@intel.com>
Acked-by: Hyong Youb Kim <hyonkim@cisco.com>
Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>
Reviewed-by: Andrzej Ostruszka <aostruszka@marvell.com>
Acked-by: David Marchand <david.marchand@redhat.com>
When setting the CONFIG_RTE_BUILD_SHARED_LIB to y,
and build the mlx5 pmd, there is a building error.
To fix it, add RTE_IBVERBS_LINK_DLOPEN to include
relative codes.
mlx5_common.o: In function `mlx5_glue_init':
drivers/common/mlx5/mlx5_common.c:324: undefined reference to `dlclose'
Fixes: 7b4f1e6bd3 ("common/mlx5: introduce common library")
Cc: stable@dpdk.org
Signed-off-by: Tonghao Zhang <xiangxia.m.yue@gmail.com>
Tested-by: Ali Alnubani <alialnu@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
This patch adds to MLX5 PMD the support of matching on IPv4 TTL and
IPv6 hoplimit.
Support is valid when using DV flow engine (Verbs flow engine doesn't
support matching on this field).
Signed-off-by: Eli Britstein <elibr@mellanox.com>
Signed-off-by: Dekel Peled <dekelp@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
The rte_pci.h file includes more header files than are actually needed,
which means that all users of it also include those headers. This patch
removes the unneeded headers - adding them elsewhere where other components
were requiring them but not including them directly.
Fixes: c752998b5e ("pci: introduce library and driver")
Cc: stable@dpdk.org
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
Acked-by: Thomas Monjalon <thomas@monjalon.net>
This adds new device id to the list of Mellanox devices
that runs mlx5 PMD.
- BlueField-2 integrated ConnectX-6 Dx network controller
This device is not ready yet, it is in development stage.
Signed-off-by: Raslan Darawsheh <rasland@mellanox.com>
Reviewed-by: Gavin Hu <gavin.hu@arm.com>
Acked-by: Matan Azrad <matan@mellanox.com>
PTP functionality has been broken after a change in kernel
where enum npc_kpu_lc_ltype is change to allow adjustment of
LTYPE_MASK to detect all types of IP headers.
Syncing the required changes in DPDK to fix the issue.
The kernel side changes available in marvell SDK version SDK-10.3.2.x.
Fixes: b5dc314044 ("net/octeontx2: support base PTP")
Cc: stable@dpdk.org
Signed-off-by: Harman Kalra <hkalra@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
If ibverbs_link is dlopen, the PMD and application should not
be linked with ibverbs, but the glue library is.
Unfortunately the ibverbs dependency was exported in the
variable ext_deps, so there were overlinking.
It is fixed by not exporting the dependency in ext_deps,
and recreating a limited dependency object for cflags only.
Fixes: 1dd7c7e38c ("net/mlx4: support meson build")
Fixes: 96d7c62a70 ("net/mlx5: support meson build")
Cc: stable@dpdk.org
Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
Acked-by: Bruce Richardson <bruce.richardson@intel.com>
The name of the variable pmd_dlopen is confusing because
it can be understood as true if the PMD is dlopen,
whereas it means the ibverbs glue layer is a dlopen library.
That's why it is renamed dlopen_ibverbs.
Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
Acked-by: Bruce Richardson <bruce.richardson@intel.com>
If ibverbs_link is static and the application choose to link DPDK
as static libraries, both PMD and ibverbs libraries must be linked
as static libraries. And the dependencies of ibverbs (netlink) must
still be linked as shared libraries.
Unfortunately, meson forget about the static requirement for ibverbs
when generating the .pc file.
As a result, libibverbs, libmlx4, libmlx5 are listed in Requires.private
section (allowing to be linked as shared libraries) and libnl is missing.
A fix is in progress for meson, but anyway we will have to live without
such a fix until a better version of meson is widely available:
https://github.com/mesonbuild/meson/pull/6393
In order to avoid meson suggesting shared libraries in the section
Requires.private of the .pc file, the dependency object is recreated
with declare_dependency():
- cflags are extracted the libibverbs.pc
- ldflags, from libibverbs.pc, are processed to force
static flavor of ibverbs libraries, thanks to this syntax:
-l:libfoo.a
Fixes: 6affeabaf3 ("net/mlx: add static ibverbs linkage with meson")
Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
The libibverbs (and libmlx4/5) can be statically embedded
in the shared PMD library, or in the application with the static PMD.
It was supported with make build system in
commit 2c0dd7b69f ("config: add static linkage of mlx dependency").
The same feature is enabled with meson when using pkg-config
(i.e. only if the call to dependency() is successful).
The fallback method for searching library with cc.find_library()
is not supported because the dependencies of the found library
would not be linked (no such info in .a file unlike .so).
The main difference, in meson build system, is the generated .pc file
giving arguments to link DPDK with the application.
Unfortunately the .pc file will not keep memory of the static linkage
option for libibverbs.
Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
Acked-by: Bruce Richardson <bruce.richardson@intel.com>
The variable build is already initialized as true in
drivers/meson.build. Duplicate initializations can be removed from mlx.
When the variable build is set to false, it is easier to call
subdir_done() than branch the rest of the code on build condition.
Suggested-by: Bruce Richardson <bruce.richardson@intel.com>
Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
Acked-by: Rosen Xu <rosen.xu@intel.com>
The glue shared library name was created by the common class FMT name,
driver_name_fmt = 'rte_common_@0@', which is not correlated with
LIB_GLUE_BASE = 'librte_pmd_mlx5_glue.so'.
This causes the dynamic linkage of the glue library to fail what
remained mlx5 drivers outside the PCI driver list.
The command:
MLX5_GLUE_PATH=$(pwd)/build-meson/drivers/common/mlx5
build-meson/app/dpdk-testpmd -n 4 -w 0000:00:05.0 -w 0000:00:06.0 -- -i
The log:
common_mlx5: Cannot load glue library:
/usr/local/lib64/dpdk/pmds-20.0.1-glue/librte_pmd_mlx5_glue.so.20.02.0:
cannot open shared object file: No such file or directory
Adjust the shared library name to the LIB_GLUE_BASE definition.
Fixes: 7b4f1e6bd3 ("common/mlx5: introduce common library")
Signed-off-by: Matan Azrad <matan@mellanox.com>
To provide the better PCIe bandwidth utilization the ConnectX-4LX
NIC supports the multi-packet write (MPW) sessions allowing to
pack multiple packets into one descriptor (WQE). This is legacy
feature and it has some limitations on the packets and data
description segments. To provide the best performance all inline
packets must be put into shared data segment and the total length
of MPW session must be limited. The limit is controlled with
txq_inline_mpw devarg.
Fixes: 82e75f8323 ("net/mlx5: fix legacy multi-packet Tx descriptors")
Cc: stable@dpdk.org
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
The new symbols should be in ABI version 20.0.1.
Fixes: 89214fe915 ("net/iavf/base: move to drivers common directory")
Signed-off-by: Haiyue Wang <haiyue.wang@intel.com>
Acked-by: Xiaolong Ye <xiaolong.ye@intel.com>
Changed the ABI version to 20.0.1.
Fixes: 7b4f1e6bd3 ("common/mlx5: introduce common library")
Signed-off-by: Matan Azrad <matan@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
The header file rte_config.h is always included by make or meson.
If required in an exported API header file, it must be included
in the public header file for external applications.
In the internal files, explicit include of rte_config.h is useless,
and can be removed.
Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
Acked-by: Matan Azrad <matan@mellanox.com>
Acked-by: David Marchand <david.marchand@redhat.com>
Acked-by: Neil Horman <nhorman@tuxdriver.com>
Currently otx2_mbox_get_rsp_xxx get response once AF driver
interrupts after completion. But this function will get into
deadlock if called in another interrupt context.
To avoid it, implemented another version of this function which polls
on dedicated memory for a given timeout.
Also after clearing interrupt, there could UP messages available for
processing. So irq handler must check mbox messages.
Signed-off-by: Sunil Kumar Kori <skori@marvell.com>
Signed-off-by: Harman Kalra <hkalra@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
fill_sg_comp_from_iov() prepares gather components for i/p IOV
buffers and extra buf. This API is failing to create a gather component
for extra_buf when IOV buf len is zero. Though there is enough space
to accommodate extra_buf, because of pre-decrementing of extra_buf
length from aggregate size, this issue is seen.
Fixes: b74652f3a9 ("common/cpt: add microcode interface for encryption")
Cc: stable@dpdk.org
Signed-off-by: Archana Muniganti <marchana@marvell.com>
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Returning error when cipher and auth key are not getting set
Fixes: 6cc5409652 ("crypto/octeontx: add supported sessions")
Cc: stable@dpdk.org
Signed-off-by: Archana Muniganti <marchana@marvell.com>
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
lookup_mem provides fast accessing of data path fields.
Storing sa indices in lookup_mem which are required in
inline rx data path.
Signed-off-by: Ankur Dwivedi <adwivedi@marvell.com>
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Archana Muniganti <marchana@marvell.com>
Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
Signed-off-by: Vamsi Attunuru <vattunuru@marvell.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
Adding the infrastructure to save one opaque pointer in idev and
implement the consumer-producer in the PMDs which uses it accordingly.
Signed-off-by: Ankur Dwivedi <adwivedi@marvell.com>
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Archana Muniganti <marchana@marvell.com>
Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
Signed-off-by: Vamsi Attunuru <vattunuru@marvell.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
This routine returns true if given rte_eth_dev is security offload
capable and belongs to octeontx2.
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
Signed-off-by: Vamsi Attunuru <vattunuru@marvell.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
Adding the new mbox introduced to configure CPT LF to be used for inline
inbound.
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
As an arrangement to the vitrio queues creation, a 2 QPs and CQ may be
created for the virtio queue.
The design is to trigger an event for the guest and for the vdpa driver
when a new CQE is posted by the HW after the packet transition.
This patch add the basic operations to create and destroy the above HW
objects and to trigger the CQE events when a new CQE is posted.
Signed-off-by: Matan Azrad <matan@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Add a new driver to support vDPA operations by Mellanox devices.
The first Mellanox devices which support vDPA operations are
ConnectX-6 Dx and Bluefield1 HCA for their PF ports and VF ports.
This driver is depending on rdma-core like the mlx5 PMD, also it is
going to use mlx5 DevX to create HW objects directly by the FW.
Hence, the common/mlx5 library is linked to the mlx5_vdpa driver.
This driver will not be compiled by default due to the above
dependencies.
Register a new log type for this driver.
Signed-off-by: Matan Azrad <matan@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
Before C0 HW revision, The RSS adder was computed based the following
static formula.
rss_adder<7:0> = flow_tag<7:0> ^ flow_tag<15:8> ^
flow_tag<23:16> ^ flow_tag<31:24>
The above scheme has the following drawbacks:
1) It is not in line with other standard NIC behavior.
2) There can be an SW use case where SW can compute the hash
upfront using Toeplitz function and predict the queue selection
to optimize some packet lookup function. The nonstandard
way of doing XOR makes the consumer to not predict the queue selection.
C0 HW revision onward, The HW can configure the
rss_adder<7:0> as flow_tag<7:0> to align with standard NICs.
This patch adds an option to select legacy RSS adder mode
using tag_as_xor=1 devargs option while keeping the standard NIC
behavior as default.
Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Use the MLX5_ASSERT macros instead of the standard assert clause.
Depends on the RTE_LIBRTE_MLX5_DEBUG configuration option to define it.
If RTE_LIBRTE_MLX5_DEBUG is enabled MLX5_ASSERT is equal to RTE_VERIFY
to bypass the global CONFIG_RTE_ENABLE_ASSERT option.
If RTE_LIBRTE_MLX5_DEBUG is disabled, the global CONFIG_RTE_ENABLE_ASSERT
can still make this assert active by calling RTE_VERIFY inside RTE_ASSERT.
Signed-off-by: Alexander Kozyrev <akozyrev@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Use the RTE_LIBRTE_MLX5_DEBUG configuration flag to get rid of dependency
on the NDEBUG definition. This is a preparation step to switch
from standard assert clauses to DPDK RTE_ASSERT ones in MLX5 driver.
Signed-off-by: Alexander Kozyrev <akozyrev@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Add new 4 Netlink commands to support enable/disable ROCE:
1. mlx5_nl_devlink_family_id_get to get the Devlink family ID of
Netlink general command.
2. mlx5_nl_enable_roce_get to get the ROCE current status.
3. mlx5_nl_driver_reload - to reload the device kernel driver.
4. mlx5_nl_enable_roce_set - to set the ROCE status.
When the user changes the ROCE status, the IB device may disappear and
appear again, so DPDK driver should wait for it and to restart itself.
Signed-off-by: Matan Azrad <matan@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Move Netlink mechanism and its dependencies from net/mlx5 to
common/mlx5 in order to be ready to use by other mlx5 drivers.
The dependencies are BITFIELD defines, the ppc64 compilation workaround
for bool type and the function mlx5_translate_port_name.
Update build mechanism accordingly.
Signed-off-by: Matan Azrad <matan@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
There might be a case that one Mellanox device can be probed by
multiple mlx5 drivers.
One case is that any mlx5 vDPA device can be probed by both net/mlx5
and vdpa/mlx5.
Add a new mlx5 common API to get the requested driver by devargs:
class=[net/vdpa].
Skip net/mlx5 PMD probing while the device is selected to be probed by
the vDPA driver.
Signed-off-by: Matan Azrad <matan@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
In order to allow RQT size configuration which is limited to the
correct maximum value, add log_max_rqt_size for DevX capability
structure.
Signed-off-by: Matan Azrad <matan@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
RQ table can be changed to support different list of queues.
Add DevX command to modify DevX RQT object to point on new RQ list.
Signed-off-by: Matan Azrad <matan@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
The DevX TIR object configuration should get L3 and L4 protocols
expected to be forwarded by the TIR.
Add the PRM constant values needed to configure the L3 and L4 protocols.
Signed-off-by: Matan Azrad <matan@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Allow virtio queue type configuration in the RQ table.
The needed fields and configuration was added.
Signed-off-by: Matan Azrad <matan@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
QP creation is needed for vDPA virtq support.
Add 2 DevX commands to create QP and to modify QP state.
The support is for RC QP only in force loopback address mode.
By this way, the packets can be sent to other inernal destinations in
the nic. For example: other QPs or virtqs.
Signed-off-by: Matan Azrad <matan@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Virtio emulation offload allows SW to offload the I/O operations of a
virtio virtqueue, using the device, allowing an improved performance
for its users.
While supplying all the relevant Virtqueue information (type, size,
memory location, doorbell information, etc.). The device can then
offload the I/O operation of this queue, according to its device type
characteristics.
Some of the virtio features can be supported according to the device
capability, for example, TSO and checksum.
Add virtio queue create, modify and query DevX commands.
Signed-off-by: Matan Azrad <matan@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Virtio access region(VAR) is the UAR that allocated for virtio emulation
access.
Add rdma-core operations to allocate and free VAR.
Signed-off-by: Matan Azrad <matan@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
HW implements completion queues(CQ) used to post completion reports upon
completion of work request.
Used for Rx and Tx datapath.
Add DevX command to create a CQ.
Signed-off-by: Matan Azrad <matan@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
The isolated, protected and independent direct access to the HW by
multiple processes is implemented via User Access Region (UAR)
mechanism.
The UAR is part of PCI address space that is mapped for direct access to
the HW from the CPU.
UAR is comprised of multiple pages, each page containing registers that
control the HW operation.
UAR mechanism is used to post execution or control requests to the HW.
It is used by the HW to enforce protection and isolation between
different processes.
Add a glue command to allocate and free an UAR.
Signed-off-by: Matan Azrad <matan@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Add the next commands to glue in order to support interrupt event
channel operations associated to events in the EQ:
devx_create_event_channel,
devx_destroy_event_channel,
devx_subscribe_devx_event,
devx_subscribe_devx_event_fd,
devx_get_event.
Signed-off-by: Matan Azrad <matan@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
The event queue is managed only by the kernel.
Add the rdma-core command in glue to query the kernel event queue
details.
Signed-off-by: Matan Azrad <matan@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Add option to create an indirect mkey by the current
mlx5_devx_cmd_mkey_create command.
Indirect mkey points to set of direct mkeys.
By this way, the HW\SW can reference fragmented memory by one object.
Align the net/mlx5 driver usage in the above command.
Signed-off-by: Matan Azrad <matan@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Add support for rdma-core API to allocate NULL MR.
When the device HW get a NULL MR address, it will do nothing with the
address, no read and no write.
Signed-off-by: Matan Azrad <matan@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Add the DevX capabilities for vDPA configuration and information of
Mellanox devices.
Signed-off-by: Matan Azrad <matan@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
The CQE has owner bit to indicate if it is in SW control or HW.
Share a CQE check for all the mlx5 drivers.
Signed-off-by: Matan Azrad <matan@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Move the vendor information, vendor ID and device IDs from net/mlx5 PMD
to the common mlx5 file.
Signed-off-by: Matan Azrad <matan@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Move PCI detection by IB device from mlx5 PMD to the common code.
Signed-off-by: Matan Azrad <matan@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
A new Mellanox vdpa PMD will be added to support vdpa operations by
Mellanox adapters.
This vdpa PMD design includes mlx5_glue and mlx5_devx operations and
large parts of them are shared with the net/mlx5 PMD.
Create a new common library in drivers/common for mlx5 PMDs.
Move mlx5_glue, mlx5_devx_cmds and their dependencies to the new mlx5
common library in drivers/common.
The files mlx5_devx_cmds.c, mlx5_devx_cmds.h, mlx5_glue.c,
mlx5_glue.h and mlx5_prm.h are moved as is from drivers/net/mlx5 to
drivers/common/mlx5.
Share the log mechanism macros.
Separate also the log mechanism to allow different log level control to
the common library.
Build files and version files are adjusted accordingly.
Include lines are adjusted accordingly.
Signed-off-by: Matan Azrad <matan@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Extend RSS offload types for octeontx2. Add support to select
L3 SRC, L3 DST, L4 SRC and L4 DST for RSS calculation.
Add support to select L3 SRC or DST only, L4 SRC or DST only for RSS
calculation.
With this requirement there will be following combinations,
IPV[4,6]_SRC_ONLY, IPV[4,6]_DST_ONLY, [TCP,UDP,SCTP]_SRC_ONLY,
[TCP,UDP,SCTP]_DST_ONLY. So, instead of creating a bit for each
combination, we are using upper 4 bits (31:28) in the flow_key_cfg
to represent the SRC, DST selection. 31 => L3_SRC, 30 => L3_DST,
29 => L4_SRC, 28 => L4_DST. These won't be part of flow_cfg, so that
we don't need to change the existing ABI.
Signed-off-by: Kiran Kumar K <kirankumark@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
API makes think that rte_cryptodev_info_get() cannot return
a value >= 3 (RTE_CRYPTO_AEAD_LIST_END in 19.11).
20.02-rc1 was returning 3 (RTE_CRYPTO_AEAD_CHACHA20_POLY1305).
So the ABI compatibility contract was broken.
It could be solved with some function versioning,
but because a lack of time, the feature is reverted for now.
This reverts following commits:
- 6c9f3b347e ("cryptodev: add Chacha20-Poly1305 AEAD algorithm")
- 2c512e64d6 ("crypto/qat: support Chacha Poly")
- d55e01f579 ("test/crypto: add Chacha Poly cases")
Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
Register "dev_configure" API to configure/initialize the SDP
VF PCIe devices.
Signed-off-by: Mahipal Challa <mchalla@marvell.com>
Reviewed-by: Gavin Hu <gavin.hu@arm.com>
Remove the unused definitions, rewrite the IO data read/write helpers,
and put the common definitions related to RTE defines under the macro
__INTEL_NET_BASE_OSDEP__, so it works like OS(RTE) dependency.
Signed-off-by: Haiyue Wang <haiyue.wang@intel.com>
Acked-by: Xiaolong Ye <xiaolong.ye@intel.com>
Avoid using PCI subsystem device id for SoC revision
identification and just use PCI revision id to support C0 silicon.
This patch also reduces SQB threshold to 70% to have
sufficient buffer before we overflow SQ.
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
After each mbox send operation, context waits for minimum 1ms to get
corresponding response although response can come earlier.
So reducing wait time to lower granularity.
Signed-off-by: Sunil Kumar Kori <skori@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
