Commit Graph

472 Commits

Author SHA1 Message Date
Qi Zhang
bd885ab120 net/ice/base: use package info from ice segment metadata
There are two package versions in the package binary. Today, these two
version numbers are the same. However, in the future that may change.

Update code to use the package info from the ice segment metadata
section, which is the package information that is actually downloaded to
the firmware during the download package process.

Signed-off-by: Dan Nowlin <dan.nowlin@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-11-03 23:35:03 +01:00
Qi Zhang
b298908229 net/ice/base: add more capability to admin queue
Add below 3 new capability to "Get Capabilities" AQ commands
0x000A and 0x000B.

ICE_AQC_CAPS_IWARP
ICE_AQC_CAPS_PCIE_RESET_AVOIDANCE
ICE_AQC_CAPS_NVM_MGMT

Signed-off-by: Shay Amir <shay.amir@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-11-03 23:35:03 +01:00
Qi Zhang
a85f5a914a net/ice/base: allocate and free RSS global lookup table
Currently there is no API to allocate and free a RSS global LUT.
Incoming changes to support VFs having >16 queues will require using
RSS global LUT resources. The functions included will allow a PF to
configure a RSS global LUT for VFs that request >16 queues.

Signed-off-by: Brett Creeley <brett.creeley@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-11-03 23:35:03 +01:00
Qi Zhang
a7c0c27a6b net/ice/base: read security revision
The main NVM module and the Option ROM module contain a security
revision in their CSS header. This security revision is used to
determine whether or not the signed module should be loaded at bootup.
If the module security revision is lower than the associated minimum
security revision, it will not be loaded.

The CSS header does not have a module id associated with it, and thus
requires flat NVM reads in order to access it. To do this, take
advantage of the cached bank information. Introduce a new
"ice_read_flash_module" function that takes the module and bank to read.
Implement both ice_read_active_nvm_module and
ice_read_active_orom_module. These functions will use the cached values
to determine the active bank and calculate the appropriate offset.

Using these new access functions, extract the security revision for both
the main NVM bank and the Option ROM into the associated info structure.

Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-11-03 23:35:03 +01:00
Qi Zhang
319223c4df net/ice/base: move sched function prototypes
These functions reside in ice_sched.c but the function protypes are
declared in ice_common.h. Move the function prototypes to ice_sched.h.

Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-11-03 23:35:03 +01:00
Qi Zhang
c450ea96a4 net/ice/base: rename ptype bitmap
Align all ptype bitmap to follow ice_ptypes_xxx prefix.

Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-11-03 23:35:03 +01:00
Qi Zhang
e8406591c3 net/ice/base: modify ptype bitmap for outer MAC
Add below ptypes into ice_ptypes_mac_ofos:

MAC_IPV4[6]_ESP
MAC_IPV4[6]_AH
MAC_IPV4[6]_NAT_T_ESP
MAC_IPV4[6]_NAT_T_IKE
MAC_IPV4[6]_NAT_T_KEEP
MAC_IPV4[6]_PFCP_NODE
MAC_IPV4[6]_PFCP_SESSION
MAC_IPV4[6]_L2TPV3

So above ptype can also be selected by a filter when outer mac header
is required.

Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-11-03 23:35:03 +01:00
Qi Zhang
ca180ce05b net/ice/base: add NVM write response flags
Added NVM Write Admin Command (0x703) ARQ response flags - as
returned in "Response flags" field.
Three flags are supported: POR, PERST and EMPR. All indicate the
type of reset required to get the NVM bank update effective.

Signed-off-by: Shay Amir <shay.amir@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-11-03 23:35:03 +01:00
Qi Zhang
1df9736b92 net/ice/base: support tunnel for flow director
Add struct to store outer part for tunnel rule.
Add vxlan ptype in ipv4 mac bitmap. So when create a vxlan rule, the
ptype group will be valid.

Signed-off-by: Zhirun Yan <zhirun.yan@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-11-03 23:35:03 +01:00
Simei Su
40d466fa9f net/ice: support ACL filter in DCF
Add ice_acl_create_filter to create a rule and ice_acl_destroy_filter
to destroy a rule. If a flow is matched by ACL filter, filter rule
will be set to HW. Currently IPV4/IPV4_UDP/IPV4_TCP/IPV4_SCTP pattern
and drop action are supported.

Signed-off-by: Simei Su <simei.su@intel.com>
Signed-off-by: Xuan Ding <xuan.ding@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2020-11-03 23:24:24 +01:00
Simei Su
d647871c50 net/ice/base: fix bitmap set function
This patch corrects an upper limit value in for loop.

Fixes: dd4a3cef55 ("net/ice/base: introduce and use bitmap set API")
Cc: stable@dpdk.org

Signed-off-by: Simei Su <simei.su@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2020-11-03 23:24:24 +01:00
Radu Nicolau
ad6f7399d2 net/ice: use write combining store for tail updates
Performance improvement: use a write combining store
instead of a regular mmio write to update queue tail
registers.

Signed-off-by: Radu Nicolau <radu.nicolau@intel.com>
Reviewed-by: Wenzhuo Lu <wenzhuo.lu@intel.com>
2020-10-13 14:42:02 +02:00
Qi Zhang
da598edd06 net/ice/base: preserve default aggregator VSI information
Added the change to keep the default aggregator VSI information.

Signed-off-by: Tarun Singh <tarun.k.singh@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-09-18 18:55:10 +02:00
Qi Zhang
5a141eac05 net/ice/base: rename ACL priority values
The naming convention used to shorten 'priority' is 'prio'.
Convert the ACL related entries that use 'prior' to 'prio'.

Also, as ICE_LOW, ICE_NORMAL,... are not very descriptive of what
they represent. Add 'ACL_PRIO' to help convey their use.

Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-09-18 18:55:10 +02:00
Qi Zhang
374c4bcaa0 net/ice/base: remove unnecessary conditional
These two conditional statements are unnecessary because the condition
is always true based on existing code flow.  Remove them to resolve
potential errors from some static analysis tools.

Signed-off-by: Bruce Allan <bruce.w.allan@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-09-18 18:55:10 +02:00
Qi Zhang
3fbba579a2 net/ice/base: rename function
'xtrct' or 'xtract' is currently used in the code to shorten 'extract'.
Rename ice_prgm_acl_prof_extrt() to ice_prgm_acl_prof_xtrct() so we don't
have another variation of a 'extract'.

Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-09-18 18:55:10 +02:00
Qi Zhang
8d6004858c net/ice/base: cache NVM module bank information
The ice flash contains two copies of each of the NVM, Option ROM, and
Netlist modules. Each bank has a pointer word and a size word. In order
to correctly read from the active flash bank, the driver must calculate
the offset manually.

During NVM initialization, read the Shadow RAM control word and
determine which bank is active for each NVM module. Additionally, cache
the size and pointer values for use in calculating the correct offset.

Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-09-18 18:55:10 +02:00
Qi Zhang
9ec03609d8 net/ice/base: cleanup code
Remove unnecessary mac_type check, fix couple comment, and remove
unnecessary empty line.

Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-09-18 18:55:10 +02:00
Qi Zhang
0b7de72c96 net/ice/base: remove unused parameter
remove unused parameter of ice_parse_fdir_func_caps

Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-09-18 18:55:10 +02:00
Qi Zhang
d55ca51267 net/ice/base: separate NVM version struct
The ice_nvm_info structure has become somewhat of a dumping ground for
all of the fields related to flash version. It holds the NVM version and
EETRACK id, the OptionROM info structure, the flash size, the ShadowRAM
size, and more.

A future change is going to add the ability to read the NVM version and
EETRACK ID from the inactive NVM bank. To make this simpler, it is
useful to have these NVM version info fields extracted to their own
structure.

Rename ice_nvm_info into ice_flash_info, and create a separate
ice_nvm_info structure that will contain the eetrack and NVM map
version. Move the netlist_ver structure into ice_flash_info and rename it
ice_netlist_info for consistency.

Modify the static ice_get_orom_ver_info to take the option rom structure
as a pointer. This makes it more obvious what portion of the hw struct
is being modified. Do the same for ice_get_netlist_ver_info.

Introduce a new ice_get_nvm_ver_info function, which will be similar to
ice_get_orom_ver_info and ice_get_netlist_ver_info, used to keep the NVM
version extraction code co-located.

Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-09-18 18:55:10 +02:00
Qi Zhang
ca5a25c5f0 net/ice/base: enable QinQ filter for switch advanced rule
Enable QinQ type filter for switch advanced rule, it support tunnel
and non-tunnel packet use external and inner vlan id as input set
for rules, it also support session id as input set for PPPoE rule
with QinQ flag in packet.

Signed-off-by: Wei Zhao <wei.zhao1@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-09-18 18:55:10 +02:00
Qi Zhang
2906c7eac9 net/ice/base: adjust rate limit profile ids runtime database
Moving the runtime profile ids database/storage to the hw structure.

Signed-off-by: Shibin Koikkara Reeny <shibin.koikkara.reeny@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-09-18 18:55:10 +02:00
Qi Zhang
14fa11f485 net/ice/base: change misc ACL style
This is a collection of minor ACL style changes including:

- When there is nothing to unroll, return a value directly.
- Return ICE_SUCCESS(0) in cases where an error was previously checked
  so ICE_SUCCESS is the only possible return.
- Remove unnecessary parentheses and newlines
- Move unroll of allocation to end of function and use goto on errors to
  free.
- Fix function header comment style
- Remove 'else' from an 'if else' condition where both conditions return
  a value to reduce indentation.

Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-09-18 18:55:10 +02:00
Qi Zhang
5ebb52ae42 net/ice/base: preserve NVM capabilities in safe mode
If the driver initializes in safe mode, it will call
ice_set_safe_mode_caps. This results in clearing the capabilities
structures, in order to set them up for operating in safe mode, ensuring
many features are disabled.

This has a side effect of also clearing the capability bits that relate
to NVM update. The result is that the device driver will not indicate
support for unified update, even if the firmware is capable.

Fix this by adding the relevant capability fields to the list of values
we preserve. To simplify the code, use a common_cap structure instead of
a handful of local variables. To reduce some duplication of the
capability name, introduce a couple of macros used to restore the
capabilities values from the cached copy.

Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-09-18 18:55:09 +02:00
Qi Zhang
0fceb10f6d net/ice/base: remove function ACL count query
Remove debug function ice_aq_query_acl_cntrs.

Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-09-18 18:55:09 +02:00
Qi Zhang
39a7a85680 net/ice/base: remove repeated words
A new test in checkpatch detects repeated words; cleanup all pre-existing
occurrences of those now.

Signed-off-by: Bruce Allan <bruce.w.allan@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-09-18 18:55:09 +02:00
Qi Zhang
d58cc74ebd net/ice/base: check failed acts allocation
There is no check for failed allocation of 'acts'. Add a check and
return if memory was not successfully allocated. Also, as all 'goto out'
occur after this check there is no need to perform a check for 'acts' as
we will have returned if it is not set.

Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-09-18 18:55:09 +02:00
Qi Zhang
56ec90f190 net/ice/base: move a function
Move ice_flow_get_hw_prof, this is not necessary for DPDK, just
sync the code with other compile option which ice_flow_get_hw_prof
is declared as a static function.

Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-09-18 18:55:09 +02:00
Qi Zhang
8ae56d6af0 net/ice/base: clear advanced rules in reset preparation
Clear advanced rules from SW and HW before reset.

Signed-off-by: Norbert Ciosek <norbertx.ciosek@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-09-18 18:55:09 +02:00
Qi Zhang
54d86ca587 net/ice/base: move a function
The only caller of this function is within the file so mark it as static
and move it up in the file to avoid a forward declaration.

Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-09-18 18:55:09 +02:00
Qi Zhang
e8ae33f119 net/ice/base: filter for GTPU outer IP without inner IP
Add ptype MAC_IPV4_GTPU into
ice_ptypes_ipv4_ofos, ice_ptypes_ipv4_ofos_all and ice_ipv4_ofos_no_l4

Add ptype MAC_IPV6_GTPU into
ice_ptypes_ipv6_ofos, ice_ptypes_ipv6_ofos_all and ice_ipv6_ofos_no_l4

Add ptype MAC_IPV4_GTPU and MAC_IPV6_GTPU into
the new ice_ptypes_gtpu_no_ip

So outer IP can be configured as input set for GTPU packet that without
inner IP layer.

Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-09-18 18:55:09 +02:00
Qi Zhang
ef77f2cfe9 net/ice/base: support outer IP filter for GTPC
Add ptype MAC_IPV4_GTPC_TEID and MAC_IPV4_GTPC into
ice_ptypes_ipv4_ofos, ice_ptypes_ipv4_ofos_all and ice_ipv4_ofos_no_l4

Add ptype MAC_IPV6_GTPC_TEID and MAC_IPV6_GTPC into
ice_ptypes_ipv6_ofos, ice_ptypes_ipv6_ofos_all and ice_ipv6_ofos_no_l4

So outer IP can be configured as input set for GTPC packet.

Also add MAC_IPV4_GTPC_TEID and MAC_IPV6_GTPC_TEID into
ice_ptypes_gtpc, so when ICE_FLOW_SEG_HDR_GTPC is requested, it can
take effect on all GTPC packets (with or without TEID).

Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-09-18 18:55:09 +02:00
Qi Zhang
c6048730ea net/ice/base: refactor DCB related variables
In this patch, the DCB related variables will be refactored out of the
ice_port_info_struct. The goal is to make the ice_port_info struct
cleaner.

Signed-off-by: Chinh T Cao <chinh.t.cao@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-09-18 18:55:09 +02:00
Qi Zhang
af73360557 net/ice/base: reduce profile to recip info get from firmware
Only need to get profile_to_recip info from firmware for
profiles used by switch, no need for other free profile
in order that we can reduce the time consumed when
download a switch rule.

Signed-off-by: Wei Zhao <wei.zhao1@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-09-18 18:55:09 +02:00
Qi Zhang
24b38f1ea5 net/ice/base: introduce Tx rate limiting on port level
The PSM Configuration has a Rate Limiter for each associated
switch port based on its relative speed from the total BW of
switch ports connected to LAN controller. The rate limiters
will be dynamic get readjusted if switch port speeds are
changed at the root node layer of the scheduler tree. Adding
a function to directly modify the EIR of root node.

Signed-off-by: Shibin Koikkara Reeny <shibin.koikkara.reeny@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-09-18 18:55:09 +02:00
Qi Zhang
3cd364d84b net/ice/base: join format strings to same line
When printing messages with ice_debug, align the printed string to the
origin line of the message in order to ease debugging and tracking
messages back to their source.

Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-09-18 18:55:09 +02:00
Qi Zhang
804db32db3 net/ice/base: support GTP-U type switch rule
This patch add support for GTP-U type of switch rule.
It enable all GTP-U related ptype.

Signed-off-by: Wei Zhao <wei.zhao1@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-09-18 18:55:09 +02:00
Qi Zhang
e39e66f4f4 net/ice/base: add AQ LLDP filter control command
As of NVM ver 1.7.1 there is a new AQ command to add and remove
LLDP filters for Rx flow.  This patch implements the support
structure to implement this functionality.

Signed-off-by: Dave Ertman <david.m.ertman@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-09-18 18:55:09 +02:00
Qi Zhang
1f9c73593c net/ice/base: fix abbreviations
Correct abbreviations as identified by abbrevcheck

Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-09-18 18:55:09 +02:00
Qi Zhang
bd0438d9d4 net/ice/base: introduce and use for each bit iterator
A number of code flows iterate over a block of memory to do something
for every bit set in that memory. Use existing bit operations in a new
iterator macro to make those code flows cleaner.

Signed-off-by: Bruce Allan <bruce.w.allan@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-09-18 18:55:09 +02:00
Qi Zhang
4406ca307a net/ice/base: add function header
Add a function header for ice_cfg_phy_fc()

Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-09-18 18:55:09 +02:00
Qi Zhang
6d288fa5f7 net/ice/base: introduce and use bitmap hamming weight API
Introduce ice_bitmap_hweight() and use it instead of open-coding that
functionality.

Signed-off-by: Bruce Allan <bruce.w.allan@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-09-18 18:55:09 +02:00
Qi Zhang
dd4a3cef55 net/ice/base: introduce and use bitmap set API
Introduce ice_bitmap_set() and use it instead of open-coding that
functionality.

Signed-off-by: Bruce Allan <bruce.w.allan@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-09-18 18:55:09 +02:00
Qi Zhang
170d34ac43 net/ice/base: replace single-element array hack
Convert the pre-C90-extension "C struct hack" method (using a single-
element array at the end of a structure for implementing variable-length
types) to the preferred use of C99 flexible array member.

Signed-off-by: Bruce Allan <bruce.w.allan@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-09-18 18:55:09 +02:00
Qi Zhang
3b085e6054 net/ice/base: silence static analysis warning
Sparse warns about these casts to/from restricted types which are not
actual problems; silence the warnings.

Signed-off-by: Bruce Allan <bruce.w.allan@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-09-18 18:55:09 +02:00
Qi Zhang
2fa7b31996 net/ice/base: cleanup misleading comment
The maximum Admin Queue buffer size and NVM shadow RAM sector size are
both 4 Kilobytes. Some comments refer to those as 4Kb which can be
confused with 4 Kilobits.
Update the comments to use the commonly used KB symbol instead.

Signed-off-by: Bruce Allan <bruce.w.allan@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-09-18 18:55:09 +02:00
Qi Zhang
465f3809a6 net/ice/base: clean code wrapping
To make the wrapping a little cleaner, move the variables only applicable
to ICE_FC_AUTO into that case. Also move caching of the value to only occur
on success.

Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-09-18 18:55:09 +02:00
Qi Zhang
b41ed0021f net/ice/base: cleanup stack hog
In ice_flow_add_prof_sync(), struct ice_flow_prof_params has recently
grown in size hogging stack space when allocated there.
Hogging stack space should be avoided. Change allocation to be on the
heap when needed.

Signed-off-by: Bruce Allan <bruce.w.allan@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-09-18 18:55:09 +02:00
Qi Zhang
252deadabc net/ice/base: fix issues around move nodes
1. Fixed the max children check when moving the last(8th) children. This
   allows the parent node to hold 8 children instead of 7.
2. Check whether the VSI is already part of the given aggregator subtree
   before moving it.

Fixes: 29a0c11489 ("net/ice/base: clean code")
Cc: stable@dpdk.org

Signed-off-by: Victor Raj <victor.raj@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-09-18 18:55:09 +02:00
Qi Zhang
39ecbb6be0 net/ice/base: avoid single-member variable-length structs
There are a number of structures that consist of a one-element array as the
only struct member.  Some of those are unused (ice_aqc_add_get_recipe_data,
ice_aqc_get_port_options_data, ice_aqc_dis_txq, etc.) so remove them.
Others are used to index into a buffer/array consisting of a variable
number of a different data or structure type.  Those are unnecessary since
we can use simple pointer arithmetic or index directly into the buffer to
access individual elements of the buffer/array.

Additional code cleanups were done near areas affected by this change.

Signed-off-by: Bruce Allan <bruce.w.allan@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-09-18 18:55:09 +02:00