12 Commits

Author SHA1 Message Date
Leyi Rong
808a17b3c1 net/ice: add Rx AVX512 offload path
Split AVX512 Rx data path into two, one is for basic,
the other one can support additional Rx offload features,
including Rx checksum offload, Rx vlan offload, RSS offload.

Signed-off-by: Leyi Rong <leyi.rong@intel.com>
Signed-off-by: Wenzhuo Lu <wenzhuo.lu@intel.com>
Tested-by: Qin Sun <qinx.sun@intel.com>
2021-04-16 12:44:27 +02:00
Leyi Rong
28f9002ab6 net/ice: add Tx AVX512 offload path
Add alternative Tx data path for AVX512 which can support partial
Tx offload features, including Tx checksum offload, vlan/QinQ
insertion offload.

Signed-off-by: Leyi Rong <leyi.rong@intel.com>
Signed-off-by: Wenzhuo Lu <wenzhuo.lu@intel.com>
Tested-by: Qin Sun <qinx.sun@intel.com>
2021-04-16 12:43:49 +02:00
Wenzhuo Lu
20daa1c978 net/ice: fix crash in AVX512
Fix segment fault when failing to get the memory from the pool.
If there's no memory in the default cache, fall back to the
previous process.

The previous AVX2 rearm function is changed to add some AVX512
instructions and changed to a callee of the AVX2 and AVX512
rearm functions.

Fixes: 7f85d5ebcfe1 ("net/ice: add AVX512 vector path")
Cc: stable@dpdk.org

Reported-by: David Coyle <david.coyle@intel.com>
Signed-off-by: Wenzhuo Lu <wenzhuo.lu@intel.com>
Tested-by: David Coyle <david.coyle@intel.com>
2021-04-14 14:29:30 +02:00
Murphy Yang
30dc028802 net/ice: disable IPv4 checksum offload in vector Tx
ICE choices vector TX path or basic TX path by macro
'ICE_NO_VECTOR_FLAGS'.

This patch adds 'DEV_TX_OFFLOAD_IPV4_CKSUM' in 'ICE_NO_VECTOR_FLAGS'
to make IPv4 checksum offload processed by basic TX path.

Fixes: a22483208800 ("net/ice: disable TSO offload in vector path")
Cc: stable@dpdk.org

Signed-off-by: Murphy Yang <murphyx.yang@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2021-01-13 18:51:58 +01:00
Leyi Rong
a4e480de26 net/ice: optimize Tx by using AVX512
Optimize Tx path by using AVX512 instructions and vectorize the
tx free bufs process.

Signed-off-by: Leyi Rong <leyi.rong@intel.com>
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2020-11-03 23:24:26 +01:00
Guinan Sun
62451c94ad net/ice: remove devargs for flow mark
Currently, all data paths already support flow mark, so remove devargs
"flow-mark-support". FDIR matched ID will display in verbose
when packets match the created rule.

Signed-off-by: Guinan Sun <guinanx.sun@intel.com>
Acked-by: Leyi Rong <leyi.rong@intel.com>
2020-09-18 18:55:11 +02:00
Jeff Guo
c9047db4af net/ice: fix setting L2TAG
Base on HW, if a packet is split into multiple segments, the L2TAG
should only be valid on the last Rx descriptor. So fix it by setting
L2TAG into mbuf when processing the last split packet.

Fixes: c68a52b8b38c ("net/ice: support vector SSE in Rx")
Cc: stable@dpdk.org

Signed-off-by: Jeff Guo <jia.guo@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2020-05-22 17:10:15 +02:00
Tao Zhu
a224832088 net/ice: disable TSO offload in vector path
ICE choices VECTOR TX path or Basic TX path by macro
ICE_NO_VECTOR_FLAGS.
TSO offload only processed by Basic TX path.

Fixes: f88de4694d94 ("net/ice: support Tx SSE vector")
Cc: stable@dpdk.org

Signed-off-by: Tao Zhu <taox.zhu@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2020-01-17 19:45:23 +01:00
Qi Zhang
3b4888d53d net/ice: add flow mark hint
Since not all data paths support flow mark, the driver needs
a hint from application to select the correct data path if
flow mark is required. The patch introduces a devarg
"flow-mark-support" as a workaround solution, since a standard
way is still ongoing.

Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2019-11-20 17:36:06 +01:00
Haiyue Wang
7e124ff12c net/ice: support protocol extraction per Rx queue
The ice has the feature to extract protocol fields into flex descriptor
by programming per queue. Currently, the ice PMD will put the protocol
fields into rte_mbuf::udata64 with different type format. Application
can access the protocol fields quickly.

Signed-off-by: Haiyue Wang <haiyue.wang@intel.com>
Reviewed-by: Xiaolong Ye <xiaolong.ye@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2019-10-07 15:00:56 +02:00
Wenzhuo Lu
f88de4694d net/ice: support Tx SSE vector
Signed-off-by: Wenzhuo Lu <wenzhuo.lu@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2019-03-29 17:25:31 +01:00
Wenzhuo Lu
c68a52b8b3 net/ice: support vector SSE in Rx
Signed-off-by: Wenzhuo Lu <wenzhuo.lu@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2019-03-29 17:25:31 +01:00