Commit Graph

5639 Commits

Author SHA1 Message Date
Artem V. Andreev
c24325b3c8 mempool/bucket: implement block dequeue operation
Signed-off-by: Artem V. Andreev <artem.andreev@oktetlabs.ru>
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
2018-04-26 23:34:07 +02:00
Artem V. Andreev
4ed00862c8 mempool/bucket: implement bucket mempool manager
The manager provides a way to allocate physically and virtually
contiguous set of objects.

Signed-off-by: Artem V. Andreev <artem.andreev@oktetlabs.ru>
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
2018-04-26 23:34:07 +02:00
Stephen Hemminger
733daffa98 bus/fslmc: do not log messages if bus not present
A typical distribution will compile with default config and all
buses enabled. Therefore every driver should be silent and not
log anything for this normal case.

This patch gets rid of these messages when running on basic x86
environment such as bare metal or VM.

fslmc: DPAA2: DPRC not available
fslmc: FSLMC Bus Not Available. Skipping

Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
2018-04-26 17:47:09 +02:00
Pavan Nikhilesh
13573bd3f4 event/octeontx: fix snprintf mempool name overflow
Bugzilla-ID: 28
Fixes: f874c1eb15 ("event/octeontx: create and free timer adapter")

Reported-by: Harry van Haaren <harry.van.haaren@intel.com>
Signed-off-by: Pavan Nikhilesh <pbhagavatula@caviumnetworks.com>
Tested-by: Harry van Haaren <harry.van.haaren@intel.com>
2018-04-25 16:49:17 +02:00
Gaetan Rivet
b65ecf1993 devargs: rename legacy API
The previous symbols were deprecated for two releases.
They are now marked as such and cannot be used anymore.

They are replaced by ones respecting the new namespace that are marked
experimental.

As a result, eth_dev attach and detach are slightly reworked to follow
the changes.

Signed-off-by: Gaetan Rivet <gaetan.rivet@6wind.com>
Acked-by: Thomas Monjalon <thomas@monjalon.net>
2018-04-25 04:00:37 +02:00
Gaetan Rivet
8e6c3b795e devargs: use proper namespace prefix
rte_eal_devargs is useless, rte_devargs is sufficient.

Only experimental functions are changed for now.

Signed-off-by: Gaetan Rivet <gaetan.rivet@6wind.com>
Acked-by: Thomas Monjalon <thomas@monjalon.net>
2018-04-25 04:00:22 +02:00
Gaetan Rivet
9e6b5ea992 devargs: make parsing variadic
rte_eal_devargs_parse can be used by EAL subsystems, drivers,
applications alike.

Device parameters may be presented with different structure each time;
as a single declaration string or several strings each describing
different parts of the declaration.

To simplify the use of this parsing facility, its parameters are made
variadic.

Signed-off-by: Gaetan Rivet <gaetan.rivet@6wind.com>
Acked-by: Thomas Monjalon <thomas@monjalon.net>
2018-04-25 03:58:45 +02:00
Gaetan Rivet
efbeaee040 net/vdev_netvsc: do not reference devargs list
This list should not be used by drivers.
Use the public API instead.

Signed-off-by: Gaetan Rivet <gaetan.rivet@6wind.com>
Acked-by: Thomas Monjalon <thomas@monjalon.net>
2018-04-25 03:58:11 +02:00
Gaetan Rivet
7765f0f408 bus/pci: do not reference devargs list
This list should not be used by drivers.
Use the public API instead.

Signed-off-by: Gaetan Rivet <gaetan.rivet@6wind.com>
Acked-by: Thomas Monjalon <thomas@monjalon.net>
2018-04-25 03:58:10 +02:00
Gaetan Rivet
1f6d16ee63 bus/vdev: do not reference devargs list
This list should not be operated upon by drivers.
Use the public API to achieve the same functionalities.

Signed-off-by: Gaetan Rivet <gaetan.rivet@6wind.com>
Acked-by: Jianfeng Tan <jianfeng.tan@intel.com>
Acked-by: Thomas Monjalon <thomas@monjalon.net>
2018-04-25 03:58:03 +02:00
Olivier Matz
6383d2642b eal: set name when creating a control thread
To avoid code duplication, add a parameter to rte_ctrl_thread_create()
to specify the name of the thread.

This requires to add a wrapper for the thread start routine in
rte_thread_init(), which will first wait that the thread is configured.

Signed-off-by: Olivier Matz <olivier.matz@6wind.com>
Reviewed-by: Anatoly Burakov <anatoly.burakov@intel.com>
2018-04-25 00:51:31 +02:00
Olivier Matz
9e5afc72c9 eal: add function to create control threads
Many parts of dpdk use their own management threads. Introduce a new
wrapper for thread creation that will be extended in next commits to set
the name and affinity.

To be consistent with other DPDK APIs, the return value is negative in
case of error, which was not the case for pthread_create().

Signed-off-by: Olivier Matz <olivier.matz@6wind.com>
Reviewed-by: Anatoly Burakov <anatoly.burakov@intel.com>
2018-04-25 00:51:31 +02:00
Jianfeng Tan
ee27edbe0c drivers/net: share vdev data to secondary process
dpdk-procinfo, as a secondary process, cannot fetch stats for vdev.

This patch enables that by attaching the port from the shared data.
We also fill the eth dev ops, with only some ops works in secondary
process, for example, stats_get().

Note that, we still cannot Rx/Tx packets on the ports which do not
support multi-process.

Reported-by: Signed-off-by: Vipin Varghese <vipin.varghese@intel.com>
Signed-off-by: Jianfeng Tan <jianfeng.tan@intel.com>
Reviewed-by: Qi Zhang <qi.z.zhang@intel.com>
2018-04-24 12:37:31 +02:00
Jianfeng Tan
5f19dee604 drivers/net: do not use private ethdev data
We introduced private rte_eth_dev_data to allow vdev to be created
both in primary process and secondary process(es). This is not
friendly to multi-process model, for example, it leads to port id
contention issue if two processes both find the data entry is free.

And to get stats of primary vdev in secondary, we must allocate
from the pre-defined array so that we can find it.

Suggested-by: Bruce Richardson <bruce.richardson@intel.com>
Signed-off-by: Jianfeng Tan <jianfeng.tan@intel.com>
Reviewed-by: Qi Zhang <qi.z.zhang@intel.com>
2018-04-24 12:33:51 +02:00
Jianfeng Tan
cdb068f031 bus/vdev: scan by multi-process channel
To scan the vdevs in primary, we send request to primary process
to obtain the names for vdevs.

Only the name is shared from the primary. In probe(), the device
driver is supposed to locate (or request more) the detail
information from the primary.

Signed-off-by: Jianfeng Tan <jianfeng.tan@intel.com>
Reviewed-by: Qi Zhang <qi.z.zhang@intel.com>
Reviewed-by: Anatoly Burakov <anatoly.burakov@intel.com>
2018-04-24 12:33:36 +02:00
Jianfeng Tan
35f462839b bus/vdev: add lock on device list
As we could add virtual devices from different threads now, we
add a spin lock to protect the vdev device list.

Suggested-by: Anatoly Burakov <anatoly.burakov@intel.com>
Signed-off-by: Jianfeng Tan <jianfeng.tan@intel.com>
Reviewed-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Anatoly Burakov <anatoly.burakov@intel.com>
2018-04-24 12:33:22 +02:00
Andrew Rybchenko
0c51eac502 mempool/dpaa: prepare to remove register memory area op
Populate mempool driver callback is executed a bit later than
register memory area, provides the same information and will
substitute the later since it gives more flexibility and in addition
to notification about memory area allows to customize how mempool
objects are stored in memory.

Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>
2018-04-24 02:17:43 +02:00
Andrew Rybchenko
a1c557020f mempool/octeontx: prepare to remove register memory area op
Callback to populate pool objects has all required information and
executed a bit later than register memory area callback.

Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
Acked-by: Santosh Shukla <santosh.shukla@caviumnetworks.com>
2018-04-24 02:17:43 +02:00
Andrew Rybchenko
ce1f2c61ed mempool: remove callback to get capabilities
The callback was introduced to let generic code to know octeontx
mempool driver requirements to use single physically contiguous
memory chunk to store all objects and align object address to
total object size. Now these requirements are met using a new
callbacks to calculate required memory chunk size and to populate
objects using provided memory chunk.

These capability flags are not used anywhere else.

Restricting capabilities to flags is not generic and likely to
be insufficient to describe mempool driver features. If required
in the future, API which returns structured information may be
added.

Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
Acked-by: Santosh Shukla <santosh.shukla@caviumnetworks.com>
Acked-by: Olivier Matz <olivier.matz@6wind.com>
2018-04-24 02:16:12 +02:00
Andrew Rybchenko
4143b12200 mempool: rename flag to control IOVA-contiguous objects
Flag MEMPOOL_F_NO_PHYS_CONTIG is renamed as MEMPOOL_F_NO_IOVA_CONTIG
to follow IO memory contiguous terminology.
MEMPOOL_F_NO_PHYS_CONTIG is kept for backward compatibility and
deprecated.

Suggested-by: Olivier Matz <olivier.matz@6wind.com>
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
Acked-by: Olivier Matz <olivier.matz@6wind.com>
2018-04-24 01:39:20 +02:00
Hemant Agrawal
e37effdc3d crypto/dpaa2_sec: fix HMAC supported digest sizes
For HMAC algorithms (MD5-HMAC, SHAx-HMAC), the supported
digest sizes are not a fixed value, but a range between
1 and the maximum digest size for those algorithms.

Fixes: f947fd7718 ("crypto/dpaa2_sec: fix HMAC supported key sizes")
Cc: stable@dpdk.org

Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
2018-04-23 18:20:10 +01:00
Hemant Agrawal
6c9c2e4667 crypto/dpaa_sec: fix HMAC supported digest sizes
For HMAC algorithms (MD5-HMAC, SHAx-HMAC), the supported
digest sizes are not a fixed value, but a range between
1 and the maximum digest size for those algorithms.
Also setting iv_size as 0.

Fixes: c3e85bdcc6 ("crypto/dpaa_sec: add crypto driver for NXP DPAA platform")
Cc: stable@dpdk.org

Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
2018-04-23 18:20:10 +01:00
Hemant Agrawal
f163231e7d crypto/dpaa_sec: support dynamic logging
This patch adds the support for dynamic logging in dpaa_sec.

Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
2018-04-23 18:20:10 +01:00
Pablo de Lara
17c36a6746 crypto/zuc: batch ops with same transform
The ZUC API to encrypt packets does not require the operations
to share the same key. Currently, the operations were being
batched only when they shared the same key, but this is not needed.

Instead, now operations will be batched based on the transform
(cipher only, auth only...).

Fixes: cf7685d68f ("crypto/zuc: add driver for ZUC library")
Cc: stable@dpdk.org

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>
2018-04-23 18:20:10 +01:00
Pablo de Lara
5943233a68 crypto/zuc: remove unnecessary check
When processing operations, the operation type was being
checked to avoid if it was set to NOT SUPPORTED.
In data path, doing so is not required since that is already
checked when creating the crypto session,
so that case will not ever happen.

Fixes: cf7685d68f ("crypto/zuc: add driver for ZUC library")
Cc: stable@dpdk.org

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>
2018-04-23 18:20:10 +01:00
Pablo de Lara
466dcf34d7 crypto/zuc: do not set default op status
When crypto operations are allocated from the operation
pool, their status get reset to NOT_PROCESSED.
Therefore, there is no need to set this status again.

Fixes: cf7685d68f ("crypto/zuc: add driver for ZUC library")
Cc: stable@dpdk.org

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>
2018-04-23 18:20:10 +01:00
Jay Zhou
8144eada32 crypto/virtio: support HMAC-SHA1
The AES-CBC with HMAC-SHA1 has been supported now.

Signed-off-by: Jay Zhou <jianjay.zhou@huawei.com>
Reviewed-by: Fan Zhang <roy.fan.zhang@intel.com>
2018-04-23 18:20:10 +01:00
Jay Zhou
5889e1ff44 crypto/virtio: support AES-CBC
The AES-CBC cipher only algorithm has been supported now.

Signed-off-by: Jay Zhou <jianjay.zhou@huawei.com>
Reviewed-by: Fan Zhang <roy.fan.zhang@intel.com>
2018-04-23 18:20:10 +01:00
Jay Zhou
efd3ac6b01 crypto/virtio: support stats related ops
This patch implements the statistics of the packets.

Signed-off-by: Jay Zhou <jianjay.zhou@huawei.com>
Reviewed-by: Fan Zhang <roy.fan.zhang@intel.com>
2018-04-23 18:20:10 +01:00
Jay Zhou
82adb12a1f crypto/virtio: support burst enqueue/dequeue
This patch implements the functions of virtio_crypto_pkt_tx_burst()
and virtio_crypto_pkt_rx_burst(). The encryption and decryption requests
are placed in the data queue and are ultimately handled by
the backend crypto accelerators.

Signed-off-by: Jay Zhou <jianjay.zhou@huawei.com>
Reviewed-by: Fan Zhang <roy.fan.zhang@intel.com>
2018-04-23 18:20:10 +01:00
Jay Zhou
b7fa78c7d3 crypto/virtio: support session related ops
This patch implements session related operations, which includes creating
and destroying the session. For now, it only supports the session-oriented
API implementation. The control queue used to create or destroy sessions
for symmetric algorithms.

Signed-off-by: Jay Zhou <jianjay.zhou@huawei.com>
Reviewed-by: Fan Zhang <roy.fan.zhang@intel.com>
2018-04-23 18:20:10 +01:00
Jay Zhou
6f0175ff53 crypto/virtio: support basic PMD ops
This patch implements the basic operations of virtio crypto PMD, which
includes start, stop, close, information getting, queue setup and
release of the device.
The virtio crypto device has two types of queues, data queue and
control queue. It has one data queue at least and has one and only one
control queue. For example, if a virtio crypto device has N queues,
then [0, N-2] is the data queue index, N-1 is the control
queue index.

Signed-off-by: Jay Zhou <jianjay.zhou@huawei.com>
Reviewed-by: Fan Zhang <roy.fan.zhang@intel.com>
2018-04-23 18:20:10 +01:00
Jay Zhou
25500d4b80 crypto/virtio: support device init
This patch implements the initialization of the virtio crypto device.
The virtio crypto device conforms to virtio-1.0, so this patch only
supports modern mode operation.
The cryptodev is created at the virtio crypto pci device probing stage.
The function of virtio_crypto_pkt_tx_burst() is used to burst transfer
packets and virtio_crypto_pkt_rx_burst() is used to burst receive packets.

Signed-off-by: Jay Zhou <jianjay.zhou@huawei.com>
Reviewed-by: Fan Zhang <roy.fan.zhang@intel.com>
2018-04-23 18:20:10 +01:00
Jay Zhou
8769079ae0 crypto/virtio: add virtio crypto PMD
The virtio crypto device is a virtual cryptography device
as well as a kind of virtual hardware accelerator for
virtual machines. The linux kernel virtio-crypto driver
has been merged, and this patch introduces virtio crypto
PMD to achieve better performance.

Signed-off-by: Jay Zhou <jianjay.zhou@huawei.com>
Reviewed-by: Fan Zhang <roy.fan.zhang@intel.com>
2018-04-23 18:20:10 +01:00
Fiona Trahe
9a063cf41c crypto/qat: use SPDX license
Use SPDK license for dual-licensed files
and update license date in all files

Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
2018-04-23 18:20:09 +01:00
Sunil Kumar Kori
c3b894155f crypto/dpaa2_sec: improve error handling
Fixed as reported by NXP's internal coverity.
Also part of dpdk coverity.

Coverity issue: 268331
Coverity issue: 268333

Fixes: 8d1f3a5d75 ("crypto/dpaa2_sec: support crypto operation")
Cc: stable@dpdk.org

Signed-off-by: Sunil Kumar Kori <sunil.kori@nxp.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
2018-04-23 18:20:09 +01:00
Sunil Kumar Kori
22788c2c6a crypto/dpaa_sec: improve the error checking
Reported by NXP's internal coverity

Fixes: c3e85bdcc6 ("crypto/dpaa_sec: add crypto driver for NXP DPAA platform")
Cc: stable@dpdk.org

Signed-off-by: Sunil Kumar Kori <sunil.kori@nxp.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
2018-04-23 18:20:09 +01:00
Hemant Agrawal
228e20866a crypto/dpaa2_sec: fix OP storage for physical IOVA mode
op storage in fle is just for reference for post dq.
So, don't convert it to iova mode.

Fixes: 37f96eb01b ("crypto/dpaa2_sec: support scatter gather")
Cc: stable@dpdk.org

Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
2018-04-23 18:20:09 +01:00
Akhil Goyal
7e3e2954e0 crypto/dpaa_sec: move mempool allocation to config
Currently, the context mempools are allocated during device probe. Thus,
even if the DPAA SEC devices are not used, any application would still
allocate the memory required for working with the contexts.

This patch moves the allocation to configuration time so that when the
CAAM devices are configured, this allocation would be done.

Signed-off-by: Akhil Goyal <akhil.goyal@nxp.com>
Signed-off-by: Ashish Jain <ashish.jain@nxp.com>
Tested-by: Shreyansh Jain <shreyansh.jain@nxp.com>
2018-04-23 18:20:09 +01:00
Shreyansh Jain
debef417a0 crypto/dpaa_sec: fix null check in uninit
Fixes: c3e85bdcc6 ("crypto/dpaa_sec: add crypto driver for NXP DPAA platform")
Cc: akhil.goyal@nxp.com
Cc: stable@dpdk.org

Signed-off-by: Shreyansh Jain <shreyansh.jain@nxp.com>
2018-04-23 18:20:09 +01:00
Ashish Jain
5b0f1bd36a crypto/dpaa_sec: add portal presence check
Adding a check to do portal configuration if not already
configured before packet enqueue. This check is only done
during dpaa_sec_attach_sess_q for initial packets,
so this change wont affect the data path and hence performance.

Fixes: e79416d10f ("crypto/dpaa_sec: support multiple sessions per queue pair")
Cc: stable@dpdk.org

Signed-off-by: Ashish Jain <ashish.jain@nxp.com>
2018-04-23 18:20:09 +01:00
Ashish Jain
69cb2eebd1 crypto/dpaa_sec: add macro for device name
Fixes: c3e85bdcc6 ("crypto/dpaa_sec: add crypto driver for NXP DPAA platform")
Cc: stable@dpdk.org

Signed-off-by: Ashish Jain <ashish.jain@nxp.com>
2018-04-23 18:20:09 +01:00
Ravi Kumar
6c561b03b5 crypto/ccp: support CPU based MD5 and SHA2 family
Auth operations can be performed on CPU without offloading
to CCP if CONFIG_RTE_LIBRTE_PMD_CCP_CPU_AUTH is enabled in
DPDK configuration. CCP PMD skip offloading auth operations
to hardware engines and perform them using openssl APIs.

Signed-off-by: Ravi Kumar <ravi1.kumar@amd.com>
2018-04-23 18:20:09 +01:00
Ravi Kumar
1df800f895 crypto/ccp: support SHA3 family
Add SHA3 family authentication algorithm support for
CCP crypto PMD. This patch defines new macros for SHA3
algorithms in the DPDK crypto framework.

Signed-off-by: Ravi Kumar <ravi1.kumar@amd.com>
2018-04-23 18:20:09 +01:00
Ravi Kumar
ca40ea2471 crypto/ccp: support SHA2 family
Add SHA2 family authentication algorithm support for
CCP crypto PMD.

Signed-off-by: Ravi Kumar <ravi1.kumar@amd.com>
2018-04-23 18:20:09 +01:00
Ravi Kumar
0c6a81eff1 crypto/ccp: support SHA1
Signed-off-by: Ravi Kumar <ravi1.kumar@amd.com>
2018-04-23 18:20:09 +01:00
Ravi Kumar
afc5345907 crypto/ccp: support AES-GCM
Support AES-GCM-128/192/256 AEAD algorithm for
CCP crypto PMD.

Signed-off-by: Ravi Kumar <ravi1.kumar@amd.com>
2018-04-23 18:20:09 +01:00
Ravi Kumar
687ae11f56 crypto/ccp: support AES-CMAC
Support AES-CMAC-128/192/256 authentication algorithm for
CCP crypto PMD.

Signed-off-by: Ravi Kumar <ravi1.kumar@amd.com>
2018-04-23 18:20:09 +01:00
Ravi Kumar
c05adb0603 crypto/ccp: support 3DES
Support 3DES-CBC cipher algorithm for CCP crypto PMD.

Signed-off-by: Ravi Kumar <ravi1.kumar@amd.com>
2018-04-23 18:20:09 +01:00
Ravi Kumar
d9a9e56192 crypto/ccp: support AES
Added CCP cipher support for following algorithms:
AES-CBC-128/192/256
AES-CTR-128/192/256
AES-ECB-128/192/256

Signed-off-by: Ravi Kumar <ravi1.kumar@amd.com>
2018-04-23 18:20:09 +01:00