This patch adds the capability of matching the outer IPv4
headers for GTPU flows.
Fixes: efc16c6214 ("net/ice: support flow director GTPU tunnel")
Cc: stable@dpdk.org
Signed-off-by: Chenmin Sun <chenmin.sun@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Xiaolong Ye <xiaolong.ye@intel.com>
1. Fix ice FDIR and hash flow memory leak.
2. Fix the ice definition of LIST_FOR_EACH_ENTRY_SAFE not
save tmp which cause list deletion incompletely.
Fixes: 5f0978e962 ("net/ice/base: add OS specific implementation")
Fixes: f5cafa961f ("net/ice: add flow director create and destroy")
Fixes: 5ad3db8d4b ("net/ice: enable advanced RSS")
Cc: stable@dpdk.org
Signed-off-by: Tao Zhu <taox.zhu@intel.com>
Reviewed-by: Simei Su <simei.su@intel.com>
Reviewed-by: Yahui Cao <yahui.cao@intel.com>
Acked-by: Xiaolong Ye <xiaolong.ye@intel.com>
If there's no mark action when creating a FDIR rule,
there shouldn't be FDIR flags in mbuf.
Fixes: f5cafa961f ("net/ice: add flow director create and destroy")
Fixes: bd984f155f ("net/ice/base: support FDIR")
Cc: stable@dpdk.org
Signed-off-by: Beilei Xing <beilei.xing@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
Remove the unused definitions, rewrite the IO data read/write helpers,
and put the common definitions related to RTE defines under the macro
__INTEL_NET_BASE_OSDEP__, so it works like OS(RTE) dependency.
Signed-off-by: Haiyue Wang <haiyue.wang@intel.com>
Acked-by: Xiaolong Ye <xiaolong.ye@intel.com>
Add support for 1/10G devices.
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
ice_add_mac_rule allow user to add rule to port based on
hw->port_info->lport number. Function in some case should
allow user to add filter rule on different port, write
another function which implemented that behaviour.
The same situation is which removing mac function.
Add new API function which allow user to choose port on which
rule going to be added. Leave add mac rule function that always
add rule on hw->port_info->lport to avoid changes in components
which don't need to choose different port. Also add function to
remove rule from specific port.
Alloc more switch_info structs to track separately rules for each
port. Choose switch_info struct basing on logic port number
because in FW added rules are connected with port.
Signed-off-by: Michal Swiatkowski <michal.swiatkowski@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
Change internal implementation of how FD filter programming desc
is prepared. This is to minimize the amount of code needed to prep
the FD filter programming desc (avoid memcpy, etc...) and just use
predefined shifts and mask. This type of change are needed to expedite
FD setup during data path (ADQ uses this codepath during initial
flow setup) and it will also be useful when adding side-band
flow-director filter.
Signed-off-by: Kiran Patil <kiran.patil@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
Increase the maximum time that the driver will wait for a PF reset
from 200 milliseconds to 300 milliseconds, to account for possibility
of a slightly longer than expected PF reset.
Fixes: 453d087cca ("net/ice/base: add common functions")
Cc: stable@dpdk.org
Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
In ice_prot_type_to_id routine, correct the loop limit check
to use ARRAY_SIZE instead of looking for the array element to
have a specific value.
Fixes: fed0c5ca5f ("net/ice/base: support programming a new switch recipe")
Cc: stable@dpdk.org
Signed-off-by: Dan Nowlin <dan.nowlin@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
Enable the code to clear the HW tables.
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
Change the extraction sequence generated by flow director flexbytes to
use package mac protocol. Without this change data in packet headers
cannot be used for flexbyte matching. The old extraction for flex bytes
started at the beginning of the payload which is after the header.
Signed-off-by: Henry Tieman <henry.w.tieman@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
Use a format consistent with the rest of the code.
Signed-off-by: Bruce Allan <bruce.w.allan@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
When RDMA is not enabled, when checking for completion of a CORER or
GLOBR do not wait for the PE unit to be loaded (indicated by GLNVM_ULD
register's PE_DONE bit being set) since that does not happen and will
cause issues such as failing to initialize the device.
Signed-off-by: Bruce Allan <bruce.w.allan@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
Add a feature to allow user to add switch filter using input like
MAC + VLAN (C-tag only) + L4 (TCP/UDP) port. API "ice_add_adv_rule"
is extended to handle this filter type.
Signed-off-by: Kiran Patil <kiran.patil@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
Allow tools to access register offset 0xB8188 (GLGEN_RSTAT) for
NVMUpdate operations. This is a read-only register, so risk of other
issues stemming from this change is low. Even so, update the write
command to prevent and reject any commands which attempt to write to
this register, just like we do for GL_HICR_EN.
Signed-off-by: Jeb Cramer <jeb.j.cramer@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
Correct an error in the IPV6 header bitmask used for programming switch
rules.
Also, change other programming switch headers to use big endian
fields in order to make setting these easier.
Fixes: 04b8ec1ea8 ("net/ice/base: add protocol structures and defines")
Cc: stable@dpdk.org
Signed-off-by: Dan Nowlin <dan.nowlin@intel.com>
Signed-off-by: Wei Zhao <wei.zhao1@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Xiaolong Ye <xiaolong.ye@intel.com>
Order intermediate VSIG list correct in order to correctly match
existing VSIG lists.
When overriding pre-existing TCAM entries, properly delete the existing
entry and remove it from the change/update list.
Fixes: 51d04e4933 ("net/ice/base: add flexible pipeline module")
Signed-off-by: Dan Nowlin <dan.nowlin@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Tested-by: Zhirun Yan <zhirun.yan@intel.com>
Add device IDs for E810_XXV.
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Xiaolong Ye <xiaolong.ye@intel.com>
When a new hash profile is created, we need to reset all related
GLQF_HSYMM registers, otherwise unexpected hash behaviour may happen
on packet that hits that profile.
The patch fixes the issue that we only do reset when symmetric hash
is required, but actually for non symmetric hash we also need this,
since GLQF_HSYMM might be polluted by previous configuration.
Fixes: ddae044035 ("net/ice/base: enable symmetric hash for RSS")
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Tested-by: Simei Su <simei.su@intel.com>
Acked-by: Xiaolong Ye <xiaolong.ye@intel.com>
A new gtp flow's profile will capture other profile's non-gtp ptypes
which is unexpected. For example, a RSS flow for inner IP / UDP on
regular tunnel packet's behaviour will be changed by a following GTP RSS
rule where inner IP is the only inputset, since all tunnel ptypes have
been shifted from the first profile to the second one.
The patch fixes the issue by correcting the ptype mapping that prevents
the ptype shift.
Fixes: d1c2f76b44 ("net/ice/base: support GTP and PPPoE protocols")
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Tested-by: Simei Su <simei.su@intel.com>
Acked-by: Xiaolong Ye <xiaolong.ye@intel.com>
Combine a couple of function definitions that can fit on one line.
RCT a variable declaration.
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
Added the GTP QFI field to the Flow director interface to allow
matching against this field. Since this field only appears in GTP
packets with extension headers, this also requires adding profile
TCAM mask matching capability. This allows comprehending different
PTYPE attributes by examining flags from the parser. Using this
method, different profiles can be used by examining flag values
from the parser.
Signed-off-by: Dan Nowlin <dan.nowlin@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
In switch rule programming, if the caller requested tunnel type of
ICE_SW_TUN_AND_NON_TUN, then the code would incorrectly attempt to
add a tunneled UDP port in the training packet, this would cause the
rule addition to fail. This patch does not attempt to add the UDP
port so that the rule programming will succeed.
Fixes: c3d6ac02c0 ("net/ice/base: update switch training packets with open ports")
Signed-off-by: Dan Nowlin <dan.nowlin@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
Correct the ordering of raw field extraction in the field vector
by taking into account the ordering setting for requesting block.
Fixes: aa1cd410fa ("net/ice/base: add flow module")
Cc: stable@dpdk.org
Signed-off-by: Dan Nowlin <dan.nowlin@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
A switch rule with "drop" action will be overwritten by a
rule with same pattern match but with a "to queue" action.
While in an inversed flow creation sequence, the "to queue"
can't be overwritten by the "drop" rule.
The inconsistent behavior is not expected, the patch
fix the issue by preventing rule overwrite in both cases.
Fixes: fed0c5ca5f ("net/ice/base: support programming a new switch recipe")
Cc: stable@dpdk.org
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
Some functions create ice_pkg_enum structure, but it seems it's possible
some of the members are used un-initialized. So we'll initialize all
instantiations of this structure within ice_flex_pipe.c
The patch also fix header comment mismatch issue for
ice_init_prof_result_bm
Signed-off-by: Jeb Cramer <jeb.j.cramer@intel.com>
Signed-off-by: Jesse Brandeburg <jesse.brandeburg@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
The pointer cmd is set to an address of a structure, which can never be
NULL. Remove the check-for-NULL lines since it's dead code anyway.
Signed-off-by: Jeb Cramer <jeb.j.cramer@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
Currently, 3-tuple FD matching is implemented using masking. However,
this is using up twenty-four of the thirty-two FD masks available. This
patch uses the swap register more efficiently to implement the 3-tuple
matches, which saves all FD masks for other uses.
Added IPV6 versions of DSCP, TTL and Protocol fields for flow director
use.
Signed-off-by: Dan Nowlin <dan.nowlin@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
Added the training packet for GTPU TEID field to the Flow director to
allow matching against this field.
Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
In the flow API, the outer first ptype bitmaps contained many
references to inner ptypes. Because of PTG assignments, these were
causing issues when programming rules on the inner ptypes.
For example, in RSS when programming the outer IPV6 hash fields,
it also programmed several inner IPV4 PTGs with the same extraction.
There were several ptypes that have been removed, thus this patch
removes those bits from the type bitmaps.
Signed-off-by: Dan Nowlin <dan.nowlin@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
Correct for GRE/NVGRE training packets to include the
correct protocol IDs for TCP and UDP respectively.
Fixes: b83a0c2903 ("net/ice/base: fix inner TCP and UDP support for GRE")
Cc: stable@dpdk.org
Signed-off-by: Dan Nowlin <dan.nowlin@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
Update VLAN protocol ID to correct value for single VXLAN scenario.
Fix the missing ethertype offset for PPPoE dummy packet offset to
allow matching the corresponding field.
Fixes: d1c2f76b44 ("net/ice/base: support GTP and PPPoE protocols")
Signed-off-by: Dan Nowlin <dan.nowlin@intel.com>
Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
Remove unused code.
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
Add support for IPv6 traffic class (tc) field for switch rule.
Correct ice_ipv6_hdr based on the IPv6 Protocol using bitfields.
Add big/little endian convert for tc field before it is inserted,
since tc is only one byte and also does not have a byte-aligned
offset.
Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
Before this patch, IPv4 and UDP inner hash rule will be over
written by later rules after RSS initialization phase. This is
because the PTYPE bitmap table cover some PTYPEs belong to another
PTGs. And some PTYPEs are reserved. Remove these PTYPEs in TCP,
UDP, SCTP and ipv4 bitmap table.
Fixes: aa1cd410fa ("net/ice/base: add flow module")
Signed-off-by: Zhirun Yan <zhirun.yan@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
As title says, fix an alignment issue.
Fixes: 51d04e4933 ("net/ice/base: add flexible pipeline module")
Cc: stable@dpdk.org
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
ice_cp_bitmap() already exists and should be used instead of
using ice_memcpy(). Note, there are a couple comments that suggest
using a bitmap-specific copy function, but those are not correct
since the source block of memory is not a bitmap.
Signed-off-by: Bruce Allan <bruce.w.allan@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
Remove the error log message when attempting to download a
package that has an unsupported version.
Signed-off-by: Dan Nowlin <dan.nowlin@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
Add two bytes to meet the requirement of 4 bytes alignment for dummy
packet for creating switch rule for PPPoE.
Fixes: d1c2f76b44 ("net/ice/base: support GTP and PPPoE protocols")
Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
Previously, switch code would use only pre-reserved index
slots at the end of each field vector for recipe result index
locations. This patch adds code that detects other internal
empty index slots that could potentially be used. For each
recipe that is added, a determ ination is made as to whether
any of these additional index slots alige with all the profiles
selected for the recipe; if alignment is achieved, then these
result index slots can be used.
Signed-off-by: Dan Nowlin <dan.nowlin@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
Macros no longer be used and can be removed
Signed-off-by: Bruce Allan <bruce.w.allan@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
Before this patch, RSS tunneled rules can not be destroyed at runtime.
This is because it can not find the existing matching profile for tunnels.
segs[0] should always be zero and all matched, segs[1] for inner part.
It only construct one segment.
This patch modifies construct segment in ice_rem_rss_cfg_sync() to
match ice_add_rss_cfg_sync().
Fixes: b7d34ccc47 ("net/ice/base: packet encapsulation for RSS")
Signed-off-by: Zhirun Yan <zhirun.yan@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
Before this patch, if set rule for IPv4 first and then set rule
for TCP with IPv4. The first rule for inner IP will be overwritten
by TCP rule. This is because MAC_IPV6_TUN_MAC_IPV4_PAY using the
same ptgs PTG_TUN_INNER_IPV4_OTHER with MAC_IPV4_TUN_MAC_IPV4_PAY,
this ptype should not in TCP bitmap.
Remove this bit in TCP bitmap.
Fixes: aa1cd410fa ("net/ice/base: add flow module")
Cc: stable@dpdk.org
Signed-off-by: Zhirun Yan <zhirun.yan@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
Add GTPU qfi field support for flow director. Note that for GTPU pkt,
only qfi field (6 bits) can be set for FD. The supported GTPU pkts are
defined as:
ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_UDP,
ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_TCP,
ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_ICMP,
ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_OTHER (FRAG and PAY belong to this)
Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
ice_memdup() is preferred over an alloc immediately followed by a copy.
Signed-off-by: Bruce Allan <bruce.w.allan@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
Add parameter "symm" to rss configuration APIs.
When symm is 1, Symmetric Teoplitz Hash can be enabled by
configuring GLQF_HSYMM properly.
NOTE:
Symmetric Teoplitz hash will work only if hash schema of
VSIQF_HASH_CTL be configured to 01b and it is assumed be enabled
in PMD.
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
Update FW API minor version to align to current value advertised
by FW in NVM images.
Signed-off-by: Kevin Scott <kevin.c.scott@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
Add dest MAC address support so that this field can be matched when
we set Flow Director filter with dst addr for MAC.
Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
