When multicast promiscuous was being enabled it caused the unicast
promiscuous to be disabled. This fix resolves this by setting
NIX_RX_MODE_PROMISC when eth_dev->data->promiscuous is set, regardless.
Fixes: 325d79c00a ("net/cnxk: support all multicast")
Cc: stable@dpdk.org
Signed-off-by: Asaf Ravid <aravid@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Add support for the imissed counter using the DevX API on Windows.
imissed is queried by creating a queue counter for the port, attaching
it to all created RQs and querying the "out_of_buffer" field.
If the counter cannot be created, imissed will always report 0.
Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
The rte_kvargs_parse function parses the arguments
"key=value,key=value,..." string and return an allocated structure that
contains a key/value list.
It enables also to send a key without value and updates the values in
the following ways:
- "key=value,key,..." - value is updated as NULL.
- "key=value,key=,..." - value is updated as "" (empty string).
Mlx5 PMDs use this function to parse, but they don't support key without
value. They send the value as an argument to strtol function.
When strtol gets NULL as a parameter it cause a crash, when it gets ""
(empty string) it returns 0.
Adds a check that will prevent an argument in these formats, and returns
an error for it.
Fixes: 8520992403 ("common/mlx5: share memory related devargs")
Cc: stable@dpdk.org
Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
The common drivers_probe function calls in a loop to all probe functions
for classes requested by the user. After it manages to probe them all,
it updates this on the device in the "classes_loaded" field.
If one of them fails, all those probed to it are remove using the
drivers_remove function. However, this function only releases the
classes in the "classes_loaded" field on the given device and misses the
newly probed classes.
This patch removes the condition from the release function, and ensures
that the caller function sends a more accurate parameter.
Fixes: 8a41f4decc ("common/mlx5: introduce layer for multiple class drivers")
Cc: stable@dpdk.org
Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
ROC changes to support setting channel mask for SDP interfaces.
Signed-off-by: Satheesh Paul <psatheesh@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Wait for XAQ pool to get filled with the freed pointers
before proceeding.
Signed-off-by: Ashwin Sekhar T K <asekhar@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Wait for SQB pool to get filled with the freed pointers
before proceeding.
Signed-off-by: Ashwin Sekhar T K <asekhar@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Add roc_npa_aura_op_available_wait() API which can be used to wait
until an NPA pool gets filled up to a certain count of pointers.
Signed-off-by: Ashwin Sekhar T K <asekhar@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Use arch_extension instead of .cpu directive in NPA assembly code
snippets. Using .cpu directive with generic causes it to override
the micro architecture selected by march,mcpu.
For example if march=armv8.5-a+crypto+sve2 provided then the .cpu
directive overrides it to generic+crypto+sve2, use arch_extension
to get the expected result.
Signed-off-by: Ashwin Sekhar T K <asekhar@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Before issuing the batch alloc, we clear the first word of
cache lines so that NPA can update the status. Make sure that
this line clear is flushed before the batch alloc is issued.
Signed-off-by: Ashwin Sekhar T K <asekhar@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
When PLT_CACHE_LINE_SIZE is set to 64B, the memzone size reserved for
NPA stack could be a multiple of 64B. In such a case, when NDC SYNC
is initiated for the NPA LF, it could go and corrupt an additional
64B bytes as NDC flushes in multiples of ROC cache line size (128B).
So ensure that NPA stack size requested is a multiple of 128B.
Signed-off-by: Ashwin Sekhar T K <asekhar@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Fix the order in which layer flags and layer type fields
are parsed when dumping the MCAM data.
Fixes: 9869c39918 ("common/cnxk: support flow entry dump")
Cc: stable@dpdk.org
Signed-off-by: Satheesh Paul <psatheesh@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Some devices have a WQE size limit for striding RQ. On some newer
devices, this limitation is smaller and information on its size is
provided by the firmware.
This patch adds the attribute query from firmware: the minimum required
size of WQE buffer for striding RQ in granularity of Bytes.
Cc: stable@dpdk.org
Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
For cn9k, use HW GEN IV as default and add per pkt IV
in lookaside IPsec debug mode. Debug mode helps to verify
lookaside PMD using known outbound vectors in lookaside
autotest.
Signed-off-by: Archana Muniganti <marchana@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
Print more info when command timeout happens. Print software and
hardware queue information.
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
The memory would be updated by hardware. Use atomics to read the same.
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
Copy DF/DSCP fields would get set based on ipsec_xform in the code
preceding this. Setting it again would cause the options to be reset.
Fixes: 78d03027f2 ("common/cnxk: add IPsec common code")
Cc: stable@dpdk.org
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
MISC CPT instruction behaves differently based on minor opcode.
Define the missing minor opcodes for MISC major opcode.
Signed-off-by: Aakash Sasidharan <asasidharan@marvell.com>
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
Use the XAQ AURA create and free API while initializing the
inline device.
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Due to an errata writing to vWQE flush register might hang NIX.
Add workaround for vWQE flush hang by waiting for the max
coalescing timeout to flush out any pending vWQEs.
Fixes: ee48f711f3 ("common/cnxk: support NIX inline inbound and outbound setup")
Cc: stable@dpdk.org
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Add external clock support for cnxk timer adapter.
External clock mapping is as follows:
RTE_EVENT_TIMER_ADAPTER_EXT_CLK0 = TIM_CLK_SRC_10NS,
RTE_EVENT_TIMER_ADAPTER_EXT_CLK1 = TIM_CLK_SRC_GPIO,
RTE_EVENT_TIMER_ADAPTER_EXT_CLK2 = TIM_CLK_SRC_PTP,
RTE_EVENT_TIMER_ADAPTER_EXT_CLK3 = TIM_CLK_SRC_SYNCE,
TIM supports clock input from external GPIO, PTP, SYNCE clocks.
Input resolution is adjusted based on CNTVCT frequency for better
estimation.
Since TIM is unaware of input clock frequency, application is
expected to pass the frequency.
Example:
-a 0002:0e:00.0,tim_eclk_freq=122880000-0-0
The order of frequencies above is GPIO-PTP-SYNCE.
Signed-off-by: Shijith Thotton <sthotton@marvell.com>
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Minimum supported interval should now be retrieved from
mailbox based on the clock source and clock frequency.
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
As per the deprecation notice, In the view of enabling unified driver
for octeontx2(cn9k)/octeontx3(cn10k), removing drivers/octeontx2
drivers and replace with drivers/cnxk/ which
supports both octeontx2(cn9k) and octeontx3(cn10k) SoCs.
This patch does the following
- Replace drivers/common/octeontx2/ with drivers/common/cnxk/
- Replace drivers/mempool/octeontx2/ with drivers/mempool/cnxk/
- Replace drivers/net/octeontx2/ with drivers/net/cnxk/
- Replace drivers/event/octeontx2/ with drivers/event/cnxk/
- Replace drivers/crypto/octeontx2/ with drivers/crypto/cnxk/
- Rename config/arm/arm64_octeontx2_linux_gcc as
config/arm/arm64_cn9k_linux_gcc
- Update the documentation and MAINTAINERS to reflect the same.
- Change the reference to OCTEONTX2 as OCTEON 9. Old release notes and
the kernel related documentation is not accounted for this change.
Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Acked-by: Ferruh Yigit <ferruh.yigit@intel.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
Acked-by: Ruifeng Wang <ruifeng.wang@arm.com>
Memory region (MR) was being looked up incorrectly
for the data address of an externally-attached mbuf.
A search was attempted for the mempool of the mbuf,
while mbuf data address does not belong to this mempool
in case of externally-attached mbuf.
Only attempt the search:
1) for not externally-attached mbufs;
2) for mbufs coming from MPRQ mempool;
3) for externally-attached mbufs from mempools
with pinned external buffers.
Fixes: 08ac03580e ("common/mlx5: fix mempool registration")
Signed-off-by: Dmitry Kozlyuk <dkozlyuk@nvidia.com>
Reviewed-by: Matan Azrad <matan@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Removing the use of driver following PMD as its unnecessary.
Cc: stable@dpdk.org
Signed-off-by: Sean Morrissey <sean.morrissey@intel.com>
Signed-off-by: Conor Fogarty <conor.fogarty@intel.com>
Acked-by: John McNamara <john.mcnamara@intel.com>
Reviewed-by: Conor Walsh <conor.walsh@intel.com>
Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
Remove the use of double "the" as it does not make sense.
Cc: stable@dpdk.org
Signed-off-by: Sean Morrissey <sean.morrissey@intel.com>
Signed-off-by: Conor Fogarty <conor.fogarty@intel.com>
Acked-by: John McNamara <john.mcnamara@intel.com>
Reviewed-by: Conor Walsh <conor.walsh@intel.com>
Acked-by: Somnath Kotur <somnath.kotur@broadcom.com>
Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
Memory regions (MRs) were allocated in one chunk of memory with a
mempool registration object. However, MRs can be reused among
different mempool registrations.
When the registration that allocated the MRs originally was
destroyed, the dangling pointers to the MRs could be left in other
registrations sharing these MRs.
Splitting the memory allocation of registration structure and MRs in
this commit solves this pointer reference issue.
Fixes: 690b2a88c2 ("common/mlx5: add mempool registration facilities")
Signed-off-by: Bing Zhao <bingz@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Reviewed-by: Dmitry Kozlyuk <dkozlyuk@nvidia.com>
Mempool registration was not correctly processing
mempools with RTE_PKTMBUF_F_PINEND_EXT_BUF flag set
("pinned mempools" for short), because it is not known
at registration time whether the mempool is a pktmbuf one,
and its elements may not yet be initialized to analyze them.
Attempts had been made to recognize such pools,
but there was no robust solution, only the owner of a mempool
(the application or a device) knows its type.
This patch extends common/mlx5 registration code
to accept a hint that the mempool is a pinned one
and uses this capability from net/mlx5 driver.
1. Remove all code assuming pktmbuf pool type
or trying to recognize the type of a pool.
2. Register pinned mempools used for Rx
and their external memory on port start.
Populate the MR cache with all their MRs.
3. Change Tx slow path logic as follows:
3.1. Search the mempool database for a memory region (MR)
by the mbuf pool and its buffer address.
3.2. If not MR for the address is found for the mempool,
and the mempool contains only pinned external buffers,
perform the mempool registration of the mempool
and its external pinned memory.
3.3. Fall back to using page-based MRs in other cases
(for example, a buffer with externally attached memory,
but not from a pinned mempool).
Fixes: 690b2a88c2 ("common/mlx5: add mempool registration facilities")
Fixes: fec28ca0e3 ("net/mlx5: support mempool registration")
Signed-off-by: Dmitry Kozlyuk <dkozlyuk@nvidia.com>
Reviewed-by: Matan Azrad <matan@nvidia.com>
Reviewed-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
The "mlx5_devx_cmd_mkey_create" DevX cmd allocates DevX object using
mlx5_malloc and then creates MKey using glue function.
Compatibly, "mlx5_devx_cmd_destroy" cmd releases first the MKey using
glue function, and then free the DevX object using mlx5_free.
On Windows OS, the reg_mr function creates Mkey using
"mlx5_devx_cmd_mkey_create" cmd, but dereg_mr function using directly
glue function without freeing the object.
This behavior causes memory leak at each MR release.
In addition, the dereg_mr function makes sure that the MR pointer is
valid before destroying its fields, but always calls the memset function
that makes a difference to it.
This patch moves the dereg_mr function to use "mlx5_devx_cmd_destroy"
instead of glue function, and extends the validity test to the whole
function.
Fixes: ba42071982 ("common/mlx5: add reg/dereg MR on Windows")
Cc: stable@dpdk.org
Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
To detect the timestamp mode configured on the NIC the mlx5 PMD uses the
firmware command ACCESS_REGISTER_USER.
The HCA capability command has an attribute flag checking whether
firmware supports the command.
However, the HCA capability query command read the flag from wrong place
in PRM structure.
This patch move the flag to correct place.
Fixes: 972a1bf812 ("common/mlx5: fix user mode register access command")
Cc: stable@dpdk.org
Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
In a tunnel packet, these actions affect the inner header if
action DECAP is set; otherwise, they affect the outer header.
Adding these actions is done in two steps: add the action to
the action mask and indicate the MAC address entry ID to use.
This allows the user to check the order of actions first and
allocate resources when time comes to enable the action rule.
Signed-off-by: Ivan Malov <ivan.malov@oktetlabs.ru>
Reviewed-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
Reviewed-by: Andy Moreton <amoreton@xilinx.com>
NIC DMA memory regions API allows to establish mapping of DMA addresses
used by NIC to host IOVA understood by the host when IOMMU is absent
and NIC cannot address entire host IOVA space because of too small
DMA mask.
The API does not allow to address entire host IOVA space, but allows
arbitrary regions of the space really used for the NIC DMA.
A DMA region needs to be mapped in order to perform MCDI initialization.
Since the NIC has not been probed at that point, its configuration cannot
be accessed and there an UNKNOWN mapping type is assumed.
Signed-off-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
Reviewed-by: Andy Moreton <amoreton@xilinx.com>
Mempool registration code had a wrong assumption that it is always
dealing with packet mempools and always called rte_pktmbuf_priv_flags(),
which returned a random value for different types of mempools.
In particular, it could consider MPRQ mempools as having externally
pinned buffers, which is wrong.
Packet mempools cannot be reliably recognized, but it is sufficient to
check that the mempool is not a packet one, so it cannot have externally
pinned buffers.
Compare mempool private data size to that of packet mempools to check.
Fixes: 690b2a88c2 ("common/mlx5: add mempool registration facilities")
Fixes: fec28ca0e3 ("net/mlx5: support mempool registration")
Signed-off-by: Dmitry Kozlyuk <dkozlyuk@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Inside the MR control structure there is a pointer to the common device.
This pointer enables access to the global cache as well as hardware
objects that may be required in case a new MR needs to be created.
The purpose of adding this pointer into the MR control structure was to
avoid its transfer as a parameter to all the functions of searching MR
in the caches.
However, adding it to this structure increased the Rx and Tx data-path
structures, all the fields that followed it were slightly moved away
which caused to a reduction in performance.
This patch removes the pointer from the structure. It can be accessed
through the "dev_gen_ptr" existing field using the "container_of"
operator.
Fixes: 334ed198ab ("common/mlx5: remove redundant parameter in MR search")
Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
This commit fixes overrun of ring configuration
due to insufficient check.
Fixes: 4badfb0205 ("common/qat: fix queue pairs number")
Cc: stable@dpdk.org
Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
Acked-by: Ciara Power <ciara.power@intel.com>
Fix kasumi input len calculation to consider encr_offset.
Fixes: da39e3eccd ("common/cpt: support KASUMI")
Cc: stable@dpdk.org
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
