Change the ring logic so that the index increments
unbounded and mask it only when needed.
Modify the existing macros so that the index is not masked.
Add a new macro RING_IDX() to mask it only when needed.
Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Acked-by: Lance Richardson <lance.richardson@broadcom.com>
The fast mbuf free offload for non-vector mode requires
additional checks in order to handle long tx buffer
descriptors, so dedicated functions are needed for
vector- and non-vector-modes.
Fixes: 369f6077c5 ("net/bnxt: support fast mbuf free")
Signed-off-by: Lance Richardson <lance.richardson@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Add support for DEV_TX_OFFLOAD_MBUF_FAST_FREE to bnxt
vector mode transmit. This offload may be enabled
only when multi-segment transmit is not needed, all
transmitted mbufs for a given queue will be allocated
from the same pool, and all transmitted mbufs will
have a reference count of 1.
Signed-off-by: Lance Richardson <lance.richardson@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Simplify and optimize receive mbuf allocation function used
by the vector mode PMDs.
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Signed-off-by: Lance Richardson <lance.richardson@broadcom.com>
Improve support for small ring sizes:
- Ensure that transmit free threshold is no more than 1/4 ring size.
- Ensure that receive free threshold is no more than 1/4 ring size.
- Validate requested ring sizes against minimum supported size.
- Use rxq receive free threshold instead of fixed maximum burst
size to trigger bulk receive buffer allocation.
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Signed-off-by: Lance Richardson <lance.richardson@broadcom.com>
Add bnxt vector PMD support using NEON SIMD instructions.
Also update the 20.08 release notes with this information.
Signed-off-by: Lance Richardson <lance.richardson@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Reviewed-by: Ruifeng Wang <ruifeng.wang@arm.com>
