Commit Graph

22 Commits

Author SHA1 Message Date
Nithin Dabilpuram
aa728ea474 common/cnxk: add soft expiry poll frequency argument
Add support to override soft expiry poll frequency via devargs.
Also provide helper API to indicate reassembly support on a chip
and documentation for devargs that are already present.

Fixes: 780b9c8924 ("net/cnxk: support zero AURA for inline meta")

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
2022-10-18 12:36:21 +02:00
Rakesh Kudurumalla
4006ac1ffb common/cnxk: dump device basic information to file
Add helper API to complete device info for debug purposes.
This is used by ethdev dump API to dump ethdev's internal info.

Signed-off-by: Rakesh Kudurumalla <rkudurumalla@marvell.com>
2022-09-22 10:44:36 +02:00
Vidya Sagar Velumuri
4440eb88dd net/cnxk: use full context IPsec structures
Use the Full context SA structures and command in IPsec fast path.
For inline outbound, populate CPT instruction as per full context.
Added new macros and functions with respect to full context.

Populate WQE ptr in CPT instruction with proper offset from mbuf.
Also add option to override outbound inline SA IV for debug
Update mbuf length based on IP version in Rx post process purposes
via environment variable.

User can set env variable as:
export ETH_SEC_IV_OVR="0x0, 0x0,..."

Signed-off-by: Vidya Sagar Velumuri <vvelumuri@marvell.com>
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
2022-09-22 10:44:13 +02:00
Nithin Dabilpuram
0f3f3ad850 common/cnxk: support zero AURA for inline inbound meta
Add support to create zero aura for inline inbound meta packets when
platform supports it.

AURA zero will hold as many buffers as all the available
pkt pool with a data to accommodate 384B in best case to store
meta packets coming from Inline IPsec.

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
2022-09-22 10:44:08 +02:00
Nithin Dabilpuram
da1ec39060 common/cnxk: delay inline device RQ enable to dev start
Similar to other RQ's, delay inline device RQ until dev is started
to avoid traffic reception when device is stopped.

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
2022-09-22 10:44:03 +02:00
Nithin Dabilpuram
75315881c2 common/cnxk: use computed value for WQE skip
Use computed value for WQE skip instead of a hard-coded value.
WQE skip needs to be number of 128B lines to accommodate rte_mbuf.

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
2022-06-20 19:15:15 +02:00
Rahul Bhansali
bde0d30aed common/cnxk: print NIX inline outbound CPT LF registers
This add the support to dump NIX inline outbound CPT LF
registers.

Signed-off-by: Rahul Bhansali <rbhansali@marvell.com>
Acked-by: Ray Kinsella <mdr@ashroe.eu>
2022-06-15 14:25:50 +02:00
Nithin Dabilpuram
3c100e0e6b common/cnxk: support per-port RQ in inline device
Add support for per port RQ in inline device thereby using
Aura/Pool attributes from that port specific first RQ.
When inline device is used with channel masking, it will
fallback to single RQ for all ethdev ports.

Also remove clamping up of CQ size for LBK ethdev when
inline inbound is enabled as now backpressure is supported
even on LBK ethdevs.

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
2022-05-10 16:27:15 +02:00
Vidya Sagar Velumuri
064e790375 common/cnxk: support timestamp PKIND in CPT
Add new API to configure the SA table entries with new CPT PKIND
when timestamp is enabled.

Signed-off-by: Vidya Sagar Velumuri <vvelumuri@marvell.com>
Acked-by: Ray Kinsella <mdr@ashroe.eu>
Acked-by: Jerin Jacob <jerinj@marvell.com>
2022-05-10 16:26:48 +02:00
Vamsi Attunuru
694e29ea9b common/cnxk: fix build with custom maximum port config
Build fails with custom max eth ports configuration, like
-Dmax_ethports=1024.

Build error is:
../drivers/common/cnxk/roc_nix_inl_dev.c:794:2:
  note: in expansion of macro ‘PLT_STATIC_ASSERT’
 |  PLT_STATIC_ASSERT(sizeof(struct nix_inl_dev) <= ROC_NIX_INL_MEM_SZ);
 |  ^~~~~~~~~~~~~~~~~

Earlier soft expiry ring struct member was an array of pointers and it's
size is linked to number of RTE_MAX_ETHPORTS, and the whole struct size
is confined and protected by size assertion.
It resulted in build failure with -Dmax_ethports=1024 option and
assertion caught that failure.

Use dynamically allocated memory for storing soft expiry ring base
addresses which fixes the struct size against custom RTE_MAX_ETHPORTS
values and solves the static assertion failure.

Bugzilla ID: 940
Fixes: bea5d990a9 ("net/cnxk: support outbound soft expiry notification")
Cc: stable@dpdk.org

Reported-by: Wei Ling <weix.ling@intel.com>
Reported-by: Yu Jiang <yux.jiang@intel.com>
Signed-off-by: Vamsi Attunuru <vattunuru@marvell.com>
Signed-off-by: Srikanth Yalavarthi <syalavarthi@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
2022-03-03 06:59:25 +01:00
Vidya Sagar Velumuri
582085ed2f common/cnxk: configure reassembly parameters
When reassembly is enabled by application, set corresponding
flags in SA during creation.

Provide ROC API to configure reassembly unit with active and
zombie limits and step size.

Signed-off-by: Vidya Sagar Velumuri <vvelumuri@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
2022-02-24 21:31:53 +01:00
Vamsi Attunuru
bea5d990a9 net/cnxk: support outbound soft expiry notification
Add support for soft expiry notification mechanism in outbound
path by creating required number of ring buffers and a common poll
thread which polls for soft expiry events enqueued by microcode.

Signed-off-by: Vamsi Attunuru <vattunuru@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
2022-02-24 21:31:28 +01:00
Nithin Dabilpuram
fe5846bcc0 net/cnxk: add devargs for min-max SPI
Add support for inline inbound SPI range via devargs
instead of just max SPI value and range being 0..max.

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
2022-02-23 17:38:20 +01:00
Nithin Dabilpuram
c8c967e117 common/cnxk: support enabling AURA tail drop for RQ
Add support to enable AURA tail drop via RQ specifically
for inline device RQ's pkt pool. This is better than RQ
RED drop as it can be applied to all RQ's that are not
having security enabled but using same packet pool.

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
2022-02-23 17:35:38 +01:00
Vidya Sagar Velumuri
5ece02e736 common/cnxk: use common SA init API for default options
Use common SA init API before doing initialization based on
params. This is better so that all HW specific default values
are at single place for lookaside and inline.

Signed-off-by: Vidya Sagar Velumuri <vvelumuri@marvell.com>
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
2022-02-23 17:34:54 +01:00
Vidya Sagar Velumuri
4af4e36a93 common/cnxk: support inline device API without ROC NIX
Update the inline device functions to work when roc_nix is NULL.
This is required, as IPsec driver have to use these APIs to work
with inline IPsec device, but the IPsec driver might not have roc_nix
information.

Signed-off-by: Vidya Sagar Velumuri <vvelumuri@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
2022-02-23 17:34:44 +01:00
Nithin Dabilpuram
7e9a94909e common/cnxk: realloc inline device XAQ AURA
Add support to realloc inline device XAQ AURA with more
buffers of new packet pool AURA.

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
2022-02-23 17:34:24 +01:00
Srujana Challa
71213a8b77 common/cnxk: support CPT CTX write through microcode op
Adds APIs to write CPT CTX through microcode op(SET_CTX/WRITE_SA).

Signed-off-by: Srujana Challa <schalla@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
2021-11-03 16:05:47 +01:00
Satheesh Paul
57f7b98283 common/cnxk: support inline IPsec flow action
Add support to configure flow rules with inline IPsec action.

Signed-off-by: Satheesh Paul <psatheesh@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
2021-10-02 15:45:00 +02:00
Nithin Dabilpuram
ee48f711f3 common/cnxk: support NIX inline inbound and outbound setup
Add API to support setting up NIX inline inbound and
NIX inline outbound. In case of inbound, SA base is setup
on NIX PFFUNC and in case of outbound, required number of
CPT LF's are attached to NIX PFFUNC.

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
2021-10-02 15:44:32 +02:00
Nithin Dabilpuram
bbcd191ccf common/cnxk: support NIX inline device init and fini
Add support to init and fini inline device with NIX LF,
SSO LF and SSOW LF for inline inbound IPSec in CN10K.

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
2021-10-02 15:44:28 +02:00
Nithin Dabilpuram
cfb4f96406 common/cnxk: support NIX inline device IRQ
Add API to setup NIX inline device IRQ's. This registers
IRQ's for errors in case of NIX, CPT LF, SSOW and get wor
interrupt in case of SSO.

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
2021-10-02 15:44:25 +02:00