Commit Graph

596 Commits

Author SHA1 Message Date
Qi Zhang
fa98f411f3 net/ice/base: remove unused code for VSI list free
When free vsi list resource after vsi list update to empty, some
useless code in function ice_remove_vsi_list_rule() should be deleted.

Signed-off-by: Wei Zhao <wei.zhao1@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-06-16 19:21:08 +02:00
Qi Zhang
64767daf3c net/ice/base: add command to LLDP
Add support for LLDP forwarding to SW programming in FW
LLDP Filter Control is 0x0A0A.

Signed-off-by: Sharon Haroni <sharon.haroni@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-06-16 19:21:08 +02:00
Qi Zhang
ea88e9fc22 net/ice/base: distribute Tx queues evenly
Distribute the tx queues evenly across all queue groups. This will
help the queues to get more equal sharing among the queues when all
are in use.

In the previous algorithm, the next queue group node will be picked up
only after the previous one filled with max children.
For example: if VSI is configured with 9 queues, the first 8 queues
will be assigned to queue group 1 and the 9th queue will be assigned to
queue group 2.

The 2 queue groups split the bandwidth between them equally (50:50).
The first queue group node will share the 50% bandwidth with all of
its children (8 queues). And the second queue group node will share
the entire 50% bandwidth with its only children.

Signed-off-by: Victor Raj <victor.raj@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-06-16 19:21:08 +02:00
Qi Zhang
69e618a753 net/ice/base: adjust scheduler default bandwidth weight
By default the queues are configured in legacy mode. The default
bandwidth settings for legacy/advanced modes are different. The existing
code was using the advanced mode default value of 1 which was
incorrect. This caused the unbalanced BW sharing among siblings.
The recommended default value is applied.

Signed-off-by: Tarun Singh <tarun.k.singh@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-06-16 19:21:08 +02:00
Qi Zhang
f878b14865 net/ice/base: clear error status before set FC
ice_set_fc takes a u8 pointer 'aq_failures' as an input parameter. If
this function encounters an error, in addition to returning an
appropriate ice_status enum code, it also populates aq_failures with a
link specific error value.

If the caller does not initialize this variable to 0 before calling
ice_set_fc, it would appear as if ice_set_fc returned an error code in
this variable. So initialize it to 0.

Signed-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-06-16 19:21:08 +02:00
Qi Zhang
79d4730481 net/ice/base: avoid PPPoE IPv4 overlap
When PPPoE header is not selected, PPPoE should not be included in
ipv4 ptype bitmaps.

Signed-off-by: Yahui Cao <yahui.cao@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-06-16 19:21:08 +02:00
Qi Zhang
b952bf867f net/ice/base: support checking all autoneg enable bits
struct ice_aqc_get_phy_caps_data has multiple autoneg enable bits.
ice_is_phy_caps_an_enabled checks all bits and returns true if any
autoneg enable bits are set.

Signed-off-by: Paul Greenwalt <paul.greenwalt@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-06-16 19:21:08 +02:00
Qi Zhang
1565a51e50 net/ice/base: remove unimplemented function prototypes
There are no implementations for these two functions so remove the
prototypes.

Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-06-16 19:21:08 +02:00
Qi Zhang
8cff19be5e net/ice/base: add entries in profile TCAM with priority
The profile TCAM tables are implemented such that entries with a smaller
index in the table have a higher priority. When records to be added to
the table have flags to differentiate between standard PTG and VSIG
records, then these entries need to have higher priority in order to be
found and processed first.

Signed-off-by: Dan Nowlin <dan.nowlin@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-06-16 19:21:08 +02:00
Qi Zhang
be45049b3c net/ice/base: fix memory leak on error path
Handles memory leaks during control queue initialization and
buffer allocation failures. The MACRO - ICE_FREE_CQ_BUFS is modified to
re-use for this fix.

Fixes: 6c1f26be50 ("net/ice/base: add control queue information")
Cc: stable@dpdk.org

Signed-off-by: Surabhi Boob <surabhi.boob@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-06-16 19:21:08 +02:00
Qi Zhang
064109fd2d net/ice/base: remove unneeded variable
The variable 'adj' is initialized to 0 and later used in an addition,
but the value is never changed from 0. Remove the variable since it's
doing nothing.

Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-06-16 19:21:08 +02:00
Qi Zhang
4f13a6735f net/ice/base: fix return value
Function ice_rem_adv_rule_id return incorrect error code (ICE_ERR_PARAM)
whereas it should have returned ICE_ERR_DOES_NOT_EXIST return code
if filter list is empty or unable to find "rule" in list

Fixes: f89aa3affa ("net/ice/base: support removing advanced rule")
Cc: stable@dpdk.org

Signed-off-by: Kiran Patil <kiran.patil@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-06-16 19:21:08 +02:00
Qi Zhang
1b651a2a1d net/ice/base: update VSI handle to remaining VSI
When removing VSI from VSI list, if only one VSI left, we need
to downgrade a switch rule's action from "to VSI LIST" to "to VSI",
So, needs to update the VSI handle to the last remaining VSI for the
new action but not the first VSI be added to the list.

Signed-off-by: Haiyue Wang <haiyue.wang@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-06-16 19:21:08 +02:00
Qi Zhang
803373cc94 net/ice/base: add rate limiter profile bit mask check
Mask bits before accessing the rate limiting profile type field.

Signed-off-by: Tarun Singh <tarun.k.singh@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-06-16 19:21:08 +02:00
Qi Zhang
12b8bb04b4 net/ice/base: reset capabilities before parsing
The capability flags used to report whether an NVM component has
a pending update are stored as simple booleans. If ice_parse_caps finds
the relevant capability then the boolean is set to true.

If the capability is not provided by firmware, then the boolean value
will be left alone. This works during initialization because the
capabilities structure is zero-initialized.

However, this does not work if capabilities are updated by calling
ice_get_caps again after driver load. For example, consider if firmware
had a pending update, and then an EMPR was triggered. The update will
complete, and firmware will no longer report these capabilities.

However, the device driver will have already set the pending flags.
After an EMPR, new capabilities are read. However, because the pending
flags in the dev_caps.common_cap structure have already been set, they
will remain true.

Fix this by clearing the capabilities structures in ice_parse_caps
before processing any capabilities.

This ensures that the capabilities structure will always be refreshed to
match the state of the device or function capabilities reported by
firmware.

Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-06-16 19:21:08 +02:00
Qi Zhang
94c81be833 net/ice/base: fix advanced switch rule stale information
To avoid having stale information about "adv_rule" per recipe, when all
rules associated to a given recipe are deleted, reset the "adv_rule"
flag otherwise it causes problem later on when decisions about filter
rules being present or not are made based on "adv_rule" flag.

Removed setting "adv_rule = 1" when recipe is created. It is set
correctly when advanced switch rule is added referring to the recipe
which was created as a result of adding advanced switch rule.

Signed-off-by: Kiran Patil <kiran.patil@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-06-16 19:21:08 +02:00
Qi Zhang
8a2989969a net/ice/base: support more PPPoE packet type
This patch add more dummy packet type for PPPoE packet,
it enable tcp/udp layer of IPv4/IPv6 for PPPoE payload,
so we can use L4 dst/src port as input set for switch
filter.

Signed-off-by: Wei Zhao <wei.zhao1@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-06-16 19:21:08 +02:00
Qi Zhang
0176d92a83 net/ice/base: remove unnecessary case branches
Remove unnecessary case branch, since the switch and pipeline stage is
not designed to be handled by the flow module.

Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-06-16 19:21:08 +02:00
Qi Zhang
6bad5047be net/ice/base: return correct error code
Return ICE_ERR_DOES_NOT_EXIST return code if admin command error code is
ICE_AQ_RC_ENOENT (not exist). ice_aq_sw_rules is used when switch
rule is getting added/deleted/updated. In case of delete/update
switch rule, admin command can return ICE_AQ_RC_ENOENT error code
if such rule does not exist, hence return ICE_ERR_DOES_NOT_EXIST error
code from ice_aq_sw_rule, so that caller of this function can decide
how to handle ICE_ERR_DOES_NOT_EXIST.

Allow proper cleanup of internal data structures from ice_rem_adv_rule
function if ice_aq_sw_rules return error code ICE_ERR_DOES_NOT_EXIST
otherwise per recipe:rule list will never become empty.

Signed-off-by: Kiran Patil <kiran.patil@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-06-16 19:21:08 +02:00
Qi Zhang
6dfe33fbe5 net/ice/base: add debug logs
Add debug logs for ice_aq_get_phy_caps(), and format
ice_aq_set_phy_cfg() and ice_aq_get_link_info() debug logs to make them
more readable.

Signed-off-by: Paul Greenwalt <paul.greenwalt@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-06-16 19:21:08 +02:00
Qi Zhang
38f165b161 net/ice/base: use macro for sizeof
The definition of ICE_SW_RULE_RX_TX_ETH_HDR_SIZE open codes the size of
a structure field. Replace this with the use of FIELD_SIZEOF.

Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-06-16 19:21:08 +02:00
Qi Zhang
09ada7c890 net/ice/base: support RSS IPv6 prefix
Some IPv6 prefix related fields are defined in this patch, so that we
can use prefixes instead of full IPv6 address for RSS. These prefixes
include the first 32, 48, 64 bits of both SRC and DST IPV6 address.

Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-06-16 19:21:08 +02:00
Qi Zhang
b2d192fccd net/ice/base: adjust function signature style format
Where possible, cuddle multiple lines of function signatures to be
consistent throughout the code.

Signed-off-by: Bruce Allan <bruce.w.allan@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-06-16 19:21:08 +02:00
Qi Zhang
06d1a56251 net/ice/base: remove unnecessary braces
This patch mainly does cleanups related to unnecessary braces.
There might be different opinion to keep braces if more than
single line, but the purpose here is trying to sync DPDK's base
code with kernel's copy and its more convenient for future update.

Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-06-16 19:21:08 +02:00
Qi Zhang
9c99297895 net/ice/base: give time for package download after PF reset
To allow for resets during package download, increase the timeout period
after performing a PF Reset. The time waited is the global config lock
timeout plus the normal PFSWR timeout.

Signed-off-by: Dan Nowlin <dan.nowlin@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-06-16 19:21:08 +02:00
Qi Zhang
10fb4bb74b net/ice/base: allow GENEVE and VXLAN rules with VLAN
When programming GENEVE and VXLAN switch rules, there are some instances
where both VLAN tagged packets plus non-VLAN tagged packets are needed
to match the rule.

In order to perform this action in one rule, the switch code needs
to setup the packet flag mask to ignore the VLAN packet flag. This
will allow the rule to match both VLAN and non-VLAN packets.

Signed-off-by: Dan Nowlin <dan.nowlin@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-06-16 19:21:08 +02:00
Qi Zhang
f82d2874f8 net/ice/base: add NVM helper functions
Add couple functions that DPDK would like to use for accessing the
NVM.

Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-06-16 19:21:08 +02:00
Qi Zhang
89e27d5367 net/ice/base: initialize PHY configuration FEC fields
Currently the caller needs to initialize the ice_cfg_phy_fec() parameter
ice_aqc_set_phy_cfg_data FEC fields before calling. However, this is not
necessary since ice_cfg_phy_fec() calls Get PHY Capabilities.

Initialize ice_aqc_set_phy_cfg_data FEC capabilities and FEC option
fields from Get PHY Capabilities with media/topology in
ice_cfg_phy_fec().

Signed-off-by: Paul Greenwalt <paul.greenwalt@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-06-16 19:21:07 +02:00
Qi Zhang
aa95ac6c67 net/ice/base: add flow director completion report option
This patch introduces comp_report variable so that the called can
determine whether to report completion on error or on all cases.

Signed-off-by: Yahui Cao <yahui.cao@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-06-16 19:21:07 +02:00
Qi Zhang
086a11c7eb net/ice/base: support FDIR for L2TPV3 ESP AH and PFCP
FDIR can forward:
- L2TPV3 packets with session id.
- IPSEC ESP packets with security parameter index.
- IPSEC AH packets with security parameter index.
- NAT_T ESP packets with security parameter index.
- PFCP packets with s field value.

Signed-off-by: Yahui Cao <yahui.cao@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-06-16 19:21:07 +02:00
Qi Zhang
06dd554ac7 net/ice/base: cleanup comment formatting
Add missing space between end of comment text and comment terminator,
and remove unnecessary punctuation.

Signed-off-by: Bruce Allan <bruce.w.allan@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-06-16 19:21:07 +02:00
Qi Zhang
4003b3d7af net/ice/base: group function prototypes together
There are some function prototypes at the beginning of the file and
some at the end, group them all together so that they are in one
consistent location.

Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-06-16 19:21:07 +02:00
Qi Zhang
5ac2f0a768 net/ice/base: change IPv6 training packet
Add additional UDP payload to allow for additional headers such as ESP.

Signed-off-by: Dan Nowlin <dan.nowlin@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-06-16 19:21:07 +02:00
Qi Zhang
e2540a5a93 net/ice/base: refactor flow director filter swap
Move the swap of flow director addresses and ports into training packet
generation. This reduces the code written for ACL.

Signed-off-by: Henry Tieman <henry.w.tieman@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-06-16 19:21:07 +02:00
Qi Zhang
60ff6f5ce2 net/ice/base: consolidate VF promiscuous mode
Consolidate the Promiscuous rule for SMBM on the chosen logical port.

Signed-off-by: Shibin Koikkara Reeny <shibin.koikkara.reeny@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-06-16 19:21:07 +02:00
Qi Zhang
0bfcca26c8 net/ice/base: update maximum PHY type high index
As currently, we are supporting only 5 PHY_SPEEDs for phy_type_high.
Thus, we should adjust the value of ICE_PHY_TYPE_HIGH_MAX_INDEX to 5.

Signed-off-by: Chinh T Cao <chinh.t.cao@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-06-16 19:21:07 +02:00
Qi Zhang
89f3389295 net/ice/base: fix ACL rules index
A u8 idx in ice_acl_add_entry  causes the code to truncate the values
greater than 255 to 255 or less when calling ice_aq_program_acl_entry()
resulting in the wrong TCAM index being programmed for the specified
rule. The result is that the rule action doesn't work correctly
(packets don't get routed to the correct queue or dropped if that
is the action). Fix the issue by changing the variable to be a u16
again.

Fixes: f3202a097f ("net/ice/base: add ACL module")
Cc: stable@dpdk.org

Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-06-16 19:21:07 +02:00
Qi Zhang
f982681d84 net/ice/base: add AUI media type
Add and report AUI PHY types as an AUI media type

Signed-off-by: Doug Dziggel <douglas.a.dziggel@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-06-16 19:21:07 +02:00
Qi Zhang
4963c6ba97 net/ice/base: improve VSI filters rebuild
This change improve VSI filter configuration rebuild for
multiport configuration, ie. where 1 PF includes more than
one logical port. For some functions, association between
port and corresponding switch_info or port_info structure
has been lost because by default the pointer to the first
element of array (switch, port etc.) is passed as function
argument. With this change, pointer to proper element is
added an extra argument in relevant functions.

Signed-off-by: Grzegorz Nitka <grzegorz.nitka@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-06-16 19:21:07 +02:00
Qi Zhang
bc367c55cd net/ice/base: gate devices from FW link override
Currently, the FW link override feature is only permitted for E810
devices.  However, the ice_fw_supports_link_override() guards against FW
versions irrespective of the device. This assumes FW versions between
the families are aligned, which is not the case.

Signed-off-by: Jeb Cramer <jeb.j.cramer@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-06-16 19:21:07 +02:00
Qi Zhang
493ea93077 net/ice/base: report AOC PHY types as fiber
Report AOC types as fiber instead of unknown

Signed-off-by: Doug Dziggel <douglas.a.dziggel@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-06-16 19:21:07 +02:00
Qi Zhang
8cff0a866c net/ice/base: consolidate MAC config set
Consolidate implementation of ice_aq_set_mac_cfg for switch mode
and NIC mode. As per the specification, the driver needs to call
set_mac_cfg (opcode 0x0603) to be able to exercise jumbo frames.

Signed-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>
Signed-off-by: Jeb Cramer <jeb.j.cramer@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-06-16 19:21:07 +02:00
Qi Zhang
135ccbc6a7 net/ice/base: avoid undefined behavior
When writing the driver's struct ice_tlan_ctx structure, do not write
the 8-bit element int_q_state with the associated internal-to-hardware
field which is 122-bits, otherwise the helper function ice_write_byte()
will use undefined behavior when setting the mask used for that write.
This should not cause any functional change and will avoid use of
undefined behavior.  Also, update a comment to highlight this structure
element is not written.

Signed-off-by: Bruce Allan <bruce.w.allan@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-06-16 19:21:07 +02:00
Qi Zhang
fba97b34e5 net/ice/base: disable profile merge for flow director
For Flow Director, we don't want to re-use an existed profile with the
same field vector and mask. Merging two different flow_type’s field
vector will also make them sharing trained rule and cause rule
interference.

For example:
issue rule A: IPV4_TCP matching tcp src&dst port 80  to queue 8
issue rule B: IPV6_TCP matching tcp src&dst port 200 to queue 20
Below behavior is found but not expected:
IPV4_TCP pkt with src&dst port 200 hits rule B and goes to queue 20
IPV6_TCP pkt with src&dst port 80  hits rule A and goes to queue 8

Signed-off-by: Yahui Cao <yahui.cao@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-06-16 19:21:07 +02:00
Qi Zhang
5c58a0874e net/ice/base: add macros to parse flow director Rx desc
Add descriptor field offset and mask definition. It is used to parse
FDIR Rx descriptor field value.

Signed-off-by: Yahui Cao <yahui.cao@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-06-16 19:21:07 +02:00
Qi Zhang
1f70fb3e95 net/ice/base: support flow director for non-IP packets
FDIR can forward Ethernet packets with non-IP ethertype.

Signed-off-by: Yahui Cao <yahui.cao@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-06-16 19:21:07 +02:00
Haiyue Wang
f1f8872a79 net/ice: fix PCI DSN to lowercase
The PCI DSN (device serial number) to format package file name should be
lowercase values.

Fixes: d1c91179e9 ("net/ice: check DSN package file firstly")
Cc: stable@dpdk.org

Signed-off-by: Haiyue Wang <haiyue.wang@intel.com>
Acked-by: Xiaolong Ye <xiaolong.ye@intel.com>
2020-06-02 12:46:44 +02:00
Wei Zhao
59d3870c7f net/ice: fix switch action number check
The action number for switch filter should be 1, any
other such as 0 or more than 1 is invalid.

Fixes: 3428c6b6ec ("net/ice: add action number check for switch")
Cc: stable@dpdk.org

Signed-off-by: Wei Zhao <wei.zhao1@intel.com>
Tested-by: Qimai Xiao <qimaix.xiao@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2020-05-28 17:57:07 +02:00
Jeff Guo
c9047db4af net/ice: fix setting L2TAG
Base on HW, if a packet is split into multiple segments, the L2TAG
should only be valid on the last Rx descriptor. So fix it by setting
L2TAG into mbuf when processing the last split packet.

Fixes: c68a52b8b3 ("net/ice: support vector SSE in Rx")
Cc: stable@dpdk.org

Signed-off-by: Jeff Guo <jia.guo@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2020-05-22 17:10:15 +02:00
Qi Zhang
3ccf61bc1e net/ice/base: fix tunnel type match word handling
Use a common function when selecting the proper word and mask match for
a tunnel type when programming switch rules.

Store switch recipe field mask as little endian, which avoids needing to
convert back to big endian after reading recipe from FW.

Obtain word mask from FW recipe.

Fix word matching element and index pairing.

Fixes: fed0c5ca5f ("net/ice/base: support programming a new switch recipe")
Cc: stable@dpdk.org

Signed-off-by: Dan Nowlin <dan.nowlin@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-05-21 15:53:14 +02:00