0f91f952be
NVIDIA acquired Mellanox Technologies in 2020. The DPDK documentation and code might still include instances of or references to Mellanox trademarks (like BlueField and ConnectX) that are now NVIDIA trademarks. The PCI IDs and copyrights are unchanged. Signed-off-by: Thomas Monjalon <thomas@monjalon.net> Acked-by: Gal Cohen <galco@nvidia.com>
236 lines
9.1 KiB
ReStructuredText
236 lines
9.1 KiB
ReStructuredText
.. SPDX-License-Identifier: BSD-3-Clause
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Copyright (c) 2021 NVIDIA Corporation & Affiliates
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General-Purpose Graphics Processing Unit Library
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================================================
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When mixing networking activity with task processing on a GPU device,
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there may be the need to put in communication the CPU with the device
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in order to manage the memory, synchronize operations, exchange info, etc..
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By means of the generic GPU interface provided by this library,
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it is possible to allocate a chunk of GPU memory and use it
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to create a DPDK mempool with external mbufs having the payload
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on the GPU memory, enabling any network interface card
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supporting this feature
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to directly transmit and receive packets using GPU memory.
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Additionally, this library provides a number of functions
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to enhance the dialog between CPU and GPU.
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Out of scope of this library is to provide a wrapper for GPU specific libraries
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(e.g. CUDA Toolkit or OpenCL), thus it is not possible to launch workload
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on the device or create GPU specific objects
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(e.g. CUDA Driver context or CUDA Streams in case of NVIDIA GPUs).
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This library is optional in DPDK
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and can be disabled with ``-Ddisable_libs=gpudev``.
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Features
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--------
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This library provides a number of features:
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- Interoperability with device-specific library through generic handlers.
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- Allocate and free memory on the device.
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- Register CPU memory to make it visible from the device.
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- Communication between the CPU and the device.
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The whole CPU - GPU communication is implemented
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using CPU memory visible from the GPU.
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API Overview
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------------
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Child Device
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~~~~~~~~~~~~
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By default, DPDK PCIe module detects and registers physical GPU devices
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in the system.
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With the gpudev library is also possible to add additional non-physical devices
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through an ``uint64_t`` generic handler (e.g. CUDA Driver context)
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that will be registered internally by the driver as an additional device (child)
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connected to a physical device (parent).
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Each device (parent or child) is represented through a ID
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required to indicate which device a given operation should be executed on.
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Memory Allocation
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~~~~~~~~~~~~~~~~~
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gpudev can allocate on an input given GPU device a memory area
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returning the pointer to that memory.
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Later, it's also possible to free that memory with gpudev.
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GPU memory allocated outside of the gpudev library
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(e.g. with GPU-specific library) cannot be freed by the gpudev library.
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Memory Registration
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~~~~~~~~~~~~~~~~~~~
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gpudev can register a CPU memory area to make it visible from a GPU device.
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Later, it's also possible to unregister that memory with gpudev.
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CPU memory registered outside of the gpudev library
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(e.g. with GPU specific library) cannot be unregistered by the gpudev library.
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CPU mapping
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~~~~~~~~~~~
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gpudev can map into the CPU address space a GPU memory address allocated with gpudev.
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gpudev returns a pointer the CPU can use to access (ready or write) GPU memory.
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Later, it's also possible to unmap that memory with gpudev.
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GPU memory CPU mapped outside of the gpudev library (e.g. with GPU specific library)
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cannot be unmapped by the gpudev library.
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Memory Barrier
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~~~~~~~~~~~~~~
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Some GPU drivers may need, under certain conditions,
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to enforce the coherency of external devices writes (e.g. NIC receiving packets)
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into the GPU memory.
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gpudev abstracts and exposes this capability.
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Communication Flag
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~~~~~~~~~~~~~~~~~~
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Considering an application with some GPU task
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that's waiting to receive a signal from the CPU
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to move forward with the execution.
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The communication flag allocates a CPU memory GPU-visible ``uint32_t`` flag
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that can be used by the CPU to communicate with a GPU task.
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Communication list
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~~~~~~~~~~~~~~~~~~
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By default, DPDK pulls free mbufs from a mempool to receive packets.
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Best practice, especially in a multithreaded application,
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is to no make any assumption on which mbufs will be used
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to receive the next bursts of packets.
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Considering an application with a GPU memory mempool
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attached to a receive queue having some task waiting on the GPU
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to receive a new burst of packets to be processed,
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there is the need to communicate from the CPU
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the list of mbuf payload addresses where received packet have been stored.
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The ``rte_gpu_comm_*()`` functions are responsible to create a list of packets
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that can be populated with receive mbuf payload addresses
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and communicated to the task running on the GPU.
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CUDA Example
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------------
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In the example below, there is a pseudo-code to give an example
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about how to use functions in this library in case of a CUDA application.
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.. code-block:: c
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//////////////////////////////////////////////////////////////////////////
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///// gpudev library + CUDA functions
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//////////////////////////////////////////////////////////////////////////
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#define GPU_PAGE_SHIFT 16
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#define GPU_PAGE_SIZE (1UL << GPU_PAGE_SHIFT)
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int main()
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{
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struct rte_gpu_flag quit_flag;
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struct rte_gpu_comm_list *comm_list;
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int nb_rx = 0;
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int comm_list_entry = 0;
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struct rte_mbuf *rx_mbufs[max_rx_mbufs];
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cudaStream_t cstream;
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struct rte_mempool *mpool_payload, *mpool_header;
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struct rte_pktmbuf_extmem ext_mem;
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int16_t dev_id;
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int16_t port_id = 0;
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/* Initialize CUDA objects (cstream, context, etc..). */
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/* Use gpudev library to register a new CUDA context if any. */
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/* Let's assume the application wants to use the default context of the GPU device 0. */
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dev_id = 0;
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/* Create an external memory mempool using memory allocated on the GPU. */
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ext_mem.elt_size = mbufs_headroom_size;
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ext_mem.buf_len = RTE_ALIGN_CEIL(mbufs_num * ext_mem.elt_size, GPU_PAGE_SIZE);
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ext_mem.buf_iova = RTE_BAD_IOVA;
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ext_mem.buf_ptr = rte_gpu_mem_alloc(dev_id, ext_mem.buf_len, 0);
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rte_extmem_register(ext_mem.buf_ptr, ext_mem.buf_len, NULL, ext_mem.buf_iova, GPU_PAGE_SIZE);
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rte_dev_dma_map(rte_eth_devices[port_id].device,
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ext_mem.buf_ptr, ext_mem.buf_iova, ext_mem.buf_len);
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mpool_payload = rte_pktmbuf_pool_create_extbuf("gpu_mempool", mbufs_num,
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0, 0, ext_mem.elt_size,
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rte_socket_id(), &ext_mem, 1);
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/*
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* Create CPU - device communication flag.
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* With this flag, the CPU can tell to the CUDA kernel to exit from the main loop.
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*/
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rte_gpu_comm_create_flag(dev_id, &quit_flag, RTE_GPU_COMM_FLAG_CPU);
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rte_gpu_comm_set_flag(&quit_flag , 0);
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/*
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* Create CPU - device communication list.
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* Each entry of this list will be populated by the CPU
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* with a new set of received mbufs that the CUDA kernel has to process.
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*/
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comm_list = rte_gpu_comm_create_list(dev_id, num_entries);
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/* A very simple CUDA kernel with just 1 CUDA block and RTE_GPU_COMM_LIST_PKTS_MAX CUDA threads. */
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cuda_kernel_packet_processing<<<1, RTE_GPU_COMM_LIST_PKTS_MAX, 0, cstream>>>(quit_flag->ptr, comm_list, num_entries, ...);
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/*
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* For simplicity, the CPU here receives only 2 bursts of mbufs.
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* In a real application, network activity and device processing should overlap.
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*/
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nb_rx = rte_eth_rx_burst(port_id, queue_id, &(rx_mbufs[0]), max_rx_mbufs);
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rte_gpu_comm_populate_list_pkts(comm_list[0], rx_mbufs, nb_rx);
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nb_rx = rte_eth_rx_burst(port_id, queue_id, &(rx_mbufs[0]), max_rx_mbufs);
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rte_gpu_comm_populate_list_pkts(comm_list[1], rx_mbufs, nb_rx);
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/*
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* CPU waits for the completion of the packets' processing on the CUDA kernel
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* and then it does a cleanup of the received mbufs.
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*/
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while (rte_gpu_comm_cleanup_list(comm_list[0]));
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while (rte_gpu_comm_cleanup_list(comm_list[1]));
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/* CPU notifies the CUDA kernel that it has to terminate. */
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rte_gpu_comm_set_flag(&quit_flag, 1);
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/* gpudev objects cleanup/destruction */
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rte_gpu_mem_free(dev_id, ext_mem.buf_len);
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return 0;
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}
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//////////////////////////////////////////////////////////////////////////
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///// CUDA kernel
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//////////////////////////////////////////////////////////////////////////
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void cuda_kernel(uint32_t * quit_flag_ptr, struct rte_gpu_comm_list *comm_list, int comm_list_entries)
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{
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int comm_list_index = 0;
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struct rte_gpu_comm_pkt *pkt_list = NULL;
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/* Do some pre-processing operations. */
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/* GPU kernel keeps checking this flag to know if it has to quit or wait for more packets. */
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while (*quit_flag_ptr == 0) {
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if (comm_list[comm_list_index]->status_d[0] != RTE_GPU_COMM_LIST_READY)
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continue;
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if (threadIdx.x < comm_list[comm_list_index]->num_pkts)
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{
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/* Each CUDA thread processes a different packet. */
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packet_processing(comm_list[comm_list_index]->addr, comm_list[comm_list_index]->size, ..);
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}
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__threadfence();
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__syncthreads();
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/* Wait for new packets on the next communication list entry. */
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comm_list_index = (comm_list_index+1) % comm_list_entries;
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}
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/* Do some post-processing operations. */
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}
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