31f79cb518
Enabled the PMon for ACC100 properly.
Previous commit was missing actual implementation
and using incorrect register values.
Fixes: b4bd57b74c ("baseband/acc100: configure PMON control registers")
Signed-off-by: Hernan Vargas <hernan.vargas@intel.com>
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
185 lines
6.4 KiB
C
185 lines
6.4 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2020 Intel Corporation
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*/
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#ifndef _RTE_ACC100_PMD_H_
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#define _RTE_ACC100_PMD_H_
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#include "acc100_pf_enum.h"
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#include "acc100_vf_enum.h"
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#include "rte_acc_cfg.h"
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#include "acc_common.h"
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/* Helper macro for logging */
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#define rte_bbdev_log(level, fmt, ...) \
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rte_log(RTE_LOG_ ## level, acc100_logtype, fmt "\n", \
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##__VA_ARGS__)
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#ifdef RTE_LIBRTE_BBDEV_DEBUG
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#define rte_bbdev_log_debug(fmt, ...) \
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rte_bbdev_log(DEBUG, "acc100_pmd: " fmt, \
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##__VA_ARGS__)
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#else
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#define rte_bbdev_log_debug(fmt, ...)
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#endif
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#define ACC100_VARIANT 0
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#define ACC101_VARIANT 1
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/* ACC100 PF and VF driver names */
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#define ACC100PF_DRIVER_NAME intel_acc100_pf
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#define ACC100VF_DRIVER_NAME intel_acc100_vf
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/* ACC100 PCI vendor & device IDs */
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#define ACC100_VENDOR_ID (0x8086)
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#define ACC100_PF_DEVICE_ID (0x0d5c)
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#define ACC100_VF_DEVICE_ID (0x0d5d)
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/* Values used in writing to the registers */
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#define ACC100_REG_IRQ_EN_ALL 0x1FF83FF /* Enable all interrupts */
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/* Number of Virtual Functions ACC100 supports */
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#define ACC100_NUM_VFS 16
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#define ACC100_NUM_QGRPS 8
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#define ACC100_NUM_AQS 16
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#define ACC100_GRP_ID_SHIFT 10 /* Queue Index Hierarchy */
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#define ACC100_VF_ID_SHIFT 4 /* Queue Index Hierarchy */
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#define ACC100_WORDS_IN_ARAM_SIZE (128 * 1024 / 4)
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/* Mapping of signals for the available engines */
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#define ACC100_SIG_UL_5G 0
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#define ACC100_SIG_UL_5G_LAST 7
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#define ACC100_SIG_DL_5G 13
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#define ACC100_SIG_DL_5G_LAST 15
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#define ACC100_SIG_UL_4G 16
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#define ACC100_SIG_UL_4G_LAST 21
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#define ACC100_SIG_DL_4G 27
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#define ACC100_SIG_DL_4G_LAST 31
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#define ACC100_NUM_ACCS 5
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#define ACC100_EXT_MEM /* Default option with memory external to CPU */
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#define ACC100_HARQ_OFFSET_THRESHOLD 1024
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/* ACC100 Configuration */
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#define ACC100_DDR_ECC_ENABLE
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#define ACC100_CFG_DMA_ERROR 0x3D7
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#define ACC100_CFG_AXI_CACHE 0x11
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#define ACC100_CFG_QMGR_HI_P 0x0F0F
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#define ACC100_CFG_PCI_AXI 0xC003
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#define ACC100_CFG_PCI_BRIDGE 0x40006033
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#define ACC100_QUAD_NUMS 4
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#define ACC100_LANES_PER_QUAD 4
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#define ACC100_PCIE_LANE_OFFSET 0x200
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#define ACC100_PCIE_QUAD_OFFSET 0x2000
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#define ACC100_PCS_EQ 0x6007
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#define ACC100_ADAPT 0x8400
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#define ACC100_RESET_HI 0x20100
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#define ACC100_RESET_LO 0x20000
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#define ACC100_RESET_HARD 0x1FF
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#define ACC100_ENGINES_MAX 9
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#define ACC100_GPEX_AXIMAP_NUM 17
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#define ACC100_CLOCK_GATING_EN 0x30000
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#define ACC100_FABRIC_MODE 0xB
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/* DDR Size per VF - 512MB by default
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* Can be increased up to 4 GB with single PF/VF
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*/
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#define ACC100_HARQ_DDR (512 * 1)
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#define ACC100_PRQ_DDR_VER 0x10092020
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#define ACC100_DDR_TRAINING_MAX (5000)
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#define ACC100_HARQ_ALIGN_COMP 256
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struct acc100_registry_addr {
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unsigned int dma_ring_dl5g_hi;
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unsigned int dma_ring_dl5g_lo;
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unsigned int dma_ring_ul5g_hi;
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unsigned int dma_ring_ul5g_lo;
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unsigned int dma_ring_dl4g_hi;
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unsigned int dma_ring_dl4g_lo;
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unsigned int dma_ring_ul4g_hi;
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unsigned int dma_ring_ul4g_lo;
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unsigned int ring_size;
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unsigned int info_ring_hi;
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unsigned int info_ring_lo;
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unsigned int info_ring_en;
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unsigned int info_ring_ptr;
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unsigned int tail_ptrs_dl5g_hi;
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unsigned int tail_ptrs_dl5g_lo;
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unsigned int tail_ptrs_ul5g_hi;
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unsigned int tail_ptrs_ul5g_lo;
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unsigned int tail_ptrs_dl4g_hi;
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unsigned int tail_ptrs_dl4g_lo;
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unsigned int tail_ptrs_ul4g_hi;
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unsigned int tail_ptrs_ul4g_lo;
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unsigned int depth_log0_offset;
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unsigned int depth_log1_offset;
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unsigned int qman_group_func;
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unsigned int ddr_range;
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unsigned int pmon_ctrl_a;
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unsigned int pmon_ctrl_b;
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};
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/* Structure holding registry addresses for PF */
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static const struct acc100_registry_addr pf_reg_addr = {
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.dma_ring_dl5g_hi = HWPfDmaFec5GdlDescBaseHiRegVf,
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.dma_ring_dl5g_lo = HWPfDmaFec5GdlDescBaseLoRegVf,
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.dma_ring_ul5g_hi = HWPfDmaFec5GulDescBaseHiRegVf,
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.dma_ring_ul5g_lo = HWPfDmaFec5GulDescBaseLoRegVf,
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.dma_ring_dl4g_hi = HWPfDmaFec4GdlDescBaseHiRegVf,
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.dma_ring_dl4g_lo = HWPfDmaFec4GdlDescBaseLoRegVf,
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.dma_ring_ul4g_hi = HWPfDmaFec4GulDescBaseHiRegVf,
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.dma_ring_ul4g_lo = HWPfDmaFec4GulDescBaseLoRegVf,
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.ring_size = HWPfQmgrRingSizeVf,
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.info_ring_hi = HWPfHiInfoRingBaseHiRegPf,
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.info_ring_lo = HWPfHiInfoRingBaseLoRegPf,
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.info_ring_en = HWPfHiInfoRingIntWrEnRegPf,
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.info_ring_ptr = HWPfHiInfoRingPointerRegPf,
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.tail_ptrs_dl5g_hi = HWPfDmaFec5GdlRespPtrHiRegVf,
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.tail_ptrs_dl5g_lo = HWPfDmaFec5GdlRespPtrLoRegVf,
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.tail_ptrs_ul5g_hi = HWPfDmaFec5GulRespPtrHiRegVf,
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.tail_ptrs_ul5g_lo = HWPfDmaFec5GulRespPtrLoRegVf,
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.tail_ptrs_dl4g_hi = HWPfDmaFec4GdlRespPtrHiRegVf,
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.tail_ptrs_dl4g_lo = HWPfDmaFec4GdlRespPtrLoRegVf,
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.tail_ptrs_ul4g_hi = HWPfDmaFec4GulRespPtrHiRegVf,
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.tail_ptrs_ul4g_lo = HWPfDmaFec4GulRespPtrLoRegVf,
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.depth_log0_offset = HWPfQmgrGrpDepthLog20Vf,
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.depth_log1_offset = HWPfQmgrGrpDepthLog21Vf,
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.qman_group_func = HWPfQmgrGrpFunction0,
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.ddr_range = HWPfDmaVfDdrBaseRw,
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.pmon_ctrl_a = HWPfPermonACntrlRegVf,
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.pmon_ctrl_b = HWPfPermonBCntrlRegVf,
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};
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/* Structure holding registry addresses for VF */
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static const struct acc100_registry_addr vf_reg_addr = {
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.dma_ring_dl5g_hi = HWVfDmaFec5GdlDescBaseHiRegVf,
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.dma_ring_dl5g_lo = HWVfDmaFec5GdlDescBaseLoRegVf,
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.dma_ring_ul5g_hi = HWVfDmaFec5GulDescBaseHiRegVf,
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.dma_ring_ul5g_lo = HWVfDmaFec5GulDescBaseLoRegVf,
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.dma_ring_dl4g_hi = HWVfDmaFec4GdlDescBaseHiRegVf,
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.dma_ring_dl4g_lo = HWVfDmaFec4GdlDescBaseLoRegVf,
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.dma_ring_ul4g_hi = HWVfDmaFec4GulDescBaseHiRegVf,
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.dma_ring_ul4g_lo = HWVfDmaFec4GulDescBaseLoRegVf,
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.ring_size = HWVfQmgrRingSizeVf,
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.info_ring_hi = HWVfHiInfoRingBaseHiVf,
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.info_ring_lo = HWVfHiInfoRingBaseLoVf,
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.info_ring_en = HWVfHiInfoRingIntWrEnVf,
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.info_ring_ptr = HWVfHiInfoRingPointerVf,
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.tail_ptrs_dl5g_hi = HWVfDmaFec5GdlRespPtrHiRegVf,
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.tail_ptrs_dl5g_lo = HWVfDmaFec5GdlRespPtrLoRegVf,
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.tail_ptrs_ul5g_hi = HWVfDmaFec5GulRespPtrHiRegVf,
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.tail_ptrs_ul5g_lo = HWVfDmaFec5GulRespPtrLoRegVf,
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.tail_ptrs_dl4g_hi = HWVfDmaFec4GdlRespPtrHiRegVf,
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.tail_ptrs_dl4g_lo = HWVfDmaFec4GdlRespPtrLoRegVf,
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.tail_ptrs_ul4g_hi = HWVfDmaFec4GulRespPtrHiRegVf,
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.tail_ptrs_ul4g_lo = HWVfDmaFec4GulRespPtrLoRegVf,
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.depth_log0_offset = HWVfQmgrGrpDepthLog20Vf,
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.depth_log1_offset = HWVfQmgrGrpDepthLog21Vf,
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.qman_group_func = HWVfQmgrGrpFunction0Vf,
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.ddr_range = HWVfDmaDdrBaseRangeRoVf,
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.pmon_ctrl_a = HWVfPmACntrlRegVf,
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.pmon_ctrl_b = HWVfPmBCntrlRegVf,
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};
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#endif /* _RTE_ACC100_PMD_H_ */
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