88bde3f423
Outer Shareable Store (oshst) is sufficient for Data Memory Barrier (dmb) when doing IO on the interface via QBMAN. This will sync L3/DDR with the L1/L2 cached data. Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com> Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>
101 lines
2.7 KiB
C
101 lines
2.7 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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*
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* Copyright (c) 2008-2016 Freescale Semiconductor, Inc.
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* Copyright 2017,2021 NXP
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*
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*/
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#ifndef HEADER_COMPAT_H
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#define HEADER_COMPAT_H
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#include <stdio.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include <errno.h>
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#include <string.h>
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#include <malloc.h>
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#include <unistd.h>
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#include <linux/types.h>
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#include <rte_atomic.h>
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/* The following definitions are primarily to allow the single-source driver
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* interfaces to be included by arbitrary program code. Ie. for interfaces that
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* are also available in kernel-space, these definitions provide compatibility
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* with certain attributes and types used in those interfaces.
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*/
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/* Required compiler attributes */
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#define likely(x) __builtin_expect(!!(x), 1)
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#define unlikely(x) __builtin_expect(!!(x), 0)
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/* Required types */
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typedef uint64_t dma_addr_t;
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/* Debugging */
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#define prflush(fmt, args...) \
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do { \
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printf(fmt, ##args); \
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fflush(stdout); \
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} while (0)
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#define pr_crit(fmt, args...) prflush("CRIT:" fmt, ##args)
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#define pr_err(fmt, args...) prflush("ERR:" fmt, ##args)
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#define pr_warn(fmt, args...) prflush("WARN:" fmt, ##args)
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#define pr_info(fmt, args...) prflush(fmt, ##args)
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#ifdef RTE_LIBRTE_DPAA2_DEBUG_BUS
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/* Trace the 3 different classes of read/write access to QBMan. #undef as
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* required.
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*/
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#define QBMAN_CCSR_TRACE
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#define QBMAN_CINH_TRACE
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#define QBMAN_CENA_TRACE
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#define QBMAN_CHECKING
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#ifdef pr_debug
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#undef pr_debug
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#endif
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#define pr_debug(fmt, args...) printf(fmt, ##args)
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#define QBMAN_BUG_ON(c) \
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do { \
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static int warned_##__LINE__; \
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if ((c) && !warned_##__LINE__) { \
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pr_warn("(%s:%d)\n", __FILE__, __LINE__); \
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warned_##__LINE__ = 1; \
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} \
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} while (0)
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#else
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#define QBMAN_BUG_ON(c) {}
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#define pr_debug(fmt, args...) {}
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#endif
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/* Other miscellaneous interfaces our APIs depend on; */
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#define lower_32_bits(x) ((uint32_t)(x))
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#define upper_32_bits(x) ((uint32_t)(((x) >> 16) >> 16))
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#define __iomem
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#define __raw_readb(p) (*(const volatile unsigned char *)(p))
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#define __raw_readl(p) (*(const volatile unsigned int *)(p))
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#define __raw_writel(v, p) {*(volatile unsigned int *)(p) = (v); }
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#define dma_wmb() rte_io_wmb()
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#define atomic_t rte_atomic32_t
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#define atomic_read(v) rte_atomic32_read(v)
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#define atomic_set(v, i) rte_atomic32_set(v, i)
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#define atomic_inc(v) rte_atomic32_add(v, 1)
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#define atomic_dec(v) rte_atomic32_sub(v, 1)
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#define atomic_inc_and_test(v) rte_atomic32_inc_and_test(v)
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#define atomic_dec_and_test(v) rte_atomic32_dec_and_test(v)
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#define atomic_inc_return(v) rte_atomic32_add_return(v, 1)
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#define atomic_dec_return(v) rte_atomic32_sub_return(v, 1)
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#define atomic_sub_and_test(i, v) (rte_atomic32_sub_return(v, i) == 0)
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#endif /* HEADER_COMPAT_H */
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