a6b9d5a538
The "tx_db_nc" devarg forces doorbell register mapping to non-cached
region eliminating the extra write memory barrier. This argument was
used in creating the UAR for Tx and thus affected its performance.
Recently [1] its use has been extended to all UAR creation in all mlx5
drivers, and now its name is no longer so accurate.
This patch changes its name to "sq_db_nc" to suit any send queue that
uses it. The old name will still work for backward compatibility.
[1] commit 5dfa003db5 ("common/mlx5: fix post doorbell barrier")
Signed-off-by: Michael Baum <michaelba@nvidia.com>
Reviewed-by: Raslan Darawsheh <rasland@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
54 lines
1.5 KiB
C
54 lines
1.5 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright 2021 6WIND S.A.
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* Copyright 2021 Mellanox Technologies, Ltd
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*/
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#ifndef RTE_PMD_MLX5_COMMON_DEFS_H_
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#define RTE_PMD_MLX5_COMMON_DEFS_H_
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#include "mlx5_autoconf.h"
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/* Size of per-queue MR cache array for linear search. */
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#define MLX5_MR_CACHE_N 8
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/* Size of MR cache table for binary search. */
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#define MLX5_MR_BTREE_CACHE_N 256
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/*
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* Defines the amount of retries to allocate the first UAR in the page.
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* OFED 5.0.x and Upstream rdma_core before v29 returned the NULL as
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* UAR base address if UAR was not the first object in the UAR page.
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* It caused the PMD failure and we should try to get another UAR
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* till we get the first one with non-NULL base address returned.
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*/
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#define MLX5_ALLOC_UAR_RETRY 32
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/* Environment variable to control the doorbell register mapping. */
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#define MLX5_SHUT_UP_BF "MLX5_SHUT_UP_BF"
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#if defined(RTE_ARCH_ARM64)
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#define MLX5_SHUT_UP_BF_DEFAULT "0"
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#else
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#define MLX5_SHUT_UP_BF_DEFAULT "1"
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#endif
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/* Default PMD specific parameter value. */
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#define MLX5_ARG_UNSET (-1)
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/* MLX5_SQ_DB_NC supported values. */
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#define MLX5_SQ_DB_CACHED 0
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#define MLX5_SQ_DB_NCACHED 1
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#define MLX5_SQ_DB_HEURISTIC 2
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/* Fields of memory mapping type in offset parameter of mmap() */
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#define MLX5_UAR_MMAP_CMD_SHIFT 8
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#define MLX5_UAR_MMAP_CMD_MASK 0xff
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#ifndef HAVE_MLX5DV_MMAP_GET_NC_PAGES_CMD
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#define MLX5_MMAP_GET_NC_PAGES_CMD 3
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#endif
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#define MLX5_VDPA_MAX_RETRIES 20
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#define MLX5_VDPA_USEC 1000
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#endif /* RTE_PMD_MLX5_COMMON_DEFS_H_ */
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