32e4930d5a
Add hardware queue management code corresponding to queue pair setup and release functions. Signed-off-by: Nagadheeraj Rottela <rnagadheeraj@marvell.com> Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
166 lines
3.1 KiB
C
166 lines
3.1 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(C) 2019 Marvell International Ltd.
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*/
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#ifndef _NITROX_HAL_H_
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#define _NITROX_HAL_H_
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#include <rte_cycles.h>
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#include <rte_byteorder.h>
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#include "nitrox_csr.h"
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union nps_pkt_slc_cnts {
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uint64_t u64;
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struct {
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#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
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uint64_t slc_int : 1;
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uint64_t uns_int : 1;
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uint64_t in_int : 1;
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uint64_t mbox_int : 1;
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uint64_t resend : 1;
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uint64_t raz : 5;
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uint64_t timer : 22;
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uint64_t cnt : 32;
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#else
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uint64_t cnt : 32;
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uint64_t timer : 22;
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uint64_t raz : 5;
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uint64_t resend : 1;
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uint64_t mbox_int : 1;
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uint64_t in_int : 1;
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uint64_t uns_int : 1;
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uint64_t slc_int : 1;
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#endif
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} s;
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};
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union nps_pkt_slc_int_levels {
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uint64_t u64;
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struct {
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#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
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uint64_t bmode : 1;
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uint64_t raz : 9;
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uint64_t timet : 22;
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uint64_t cnt : 32;
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#else
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uint64_t cnt : 32;
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uint64_t timet : 22;
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uint64_t raz : 9;
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uint64_t bmode : 1;
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#endif
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} s;
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};
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union nps_pkt_slc_ctl {
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uint64_t u64;
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struct {
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#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
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uint64_t raz : 61;
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uint64_t rh : 1;
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uint64_t z : 1;
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uint64_t enb : 1;
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#else
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uint64_t enb : 1;
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uint64_t z : 1;
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uint64_t rh : 1;
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uint64_t raz : 61;
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#endif
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} s;
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};
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union nps_pkt_in_instr_ctl {
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uint64_t u64;
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struct {
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#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
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uint64_t raz : 62;
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uint64_t is64b : 1;
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uint64_t enb : 1;
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#else
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uint64_t enb : 1;
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uint64_t is64b : 1;
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uint64_t raz : 62;
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#endif
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} s;
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};
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union nps_pkt_in_instr_rsize {
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uint64_t u64;
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struct {
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#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
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uint64_t raz : 32;
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uint64_t rsize : 32;
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#else
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uint64_t rsize : 32;
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uint64_t raz : 32;
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#endif
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} s;
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};
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union nps_pkt_in_instr_baoff_dbell {
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uint64_t u64;
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struct {
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#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
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uint64_t aoff : 32;
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uint64_t dbell : 32;
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#else
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uint64_t dbell : 32;
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uint64_t aoff : 32;
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#endif
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} s;
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};
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union nps_pkt_in_done_cnts {
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uint64_t u64;
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struct {
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#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
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uint64_t slc_int : 1;
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uint64_t uns_int : 1;
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uint64_t in_int : 1;
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uint64_t mbox_int : 1;
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uint64_t resend : 1;
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uint64_t raz : 27;
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uint64_t cnt : 32;
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#else
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uint64_t cnt : 32;
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uint64_t raz : 27;
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uint64_t resend : 1;
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uint64_t mbox_int : 1;
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uint64_t in_int : 1;
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uint64_t uns_int : 1;
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uint64_t slc_int : 1;
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#endif
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} s;
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};
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union aqmq_qsz {
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uint64_t u64;
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struct {
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#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
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uint64_t raz : 32;
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uint64_t host_queue_size : 32;
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#else
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uint64_t host_queue_size : 32;
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uint64_t raz : 32;
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#endif
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} s;
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};
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enum nitrox_vf_mode {
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NITROX_MODE_PF = 0x0,
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NITROX_MODE_VF16 = 0x1,
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NITROX_MODE_VF32 = 0x2,
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NITROX_MODE_VF64 = 0x3,
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NITROX_MODE_VF128 = 0x4,
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};
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int vf_get_vf_config_mode(uint8_t *bar_addr);
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int vf_config_mode_to_nr_queues(enum nitrox_vf_mode vf_mode);
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void setup_nps_pkt_input_ring(uint8_t *bar_addr, uint16_t ring, uint32_t rsize,
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phys_addr_t raddr);
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void setup_nps_pkt_solicit_output_port(uint8_t *bar_addr, uint16_t port);
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void nps_pkt_input_ring_disable(uint8_t *bar_addr, uint16_t ring);
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void nps_pkt_solicited_port_disable(uint8_t *bar_addr, uint16_t port);
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#endif /* _NITROX_HAL_H_ */
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