7483341ae5
Currently, most ethdev callback API use queue ID as parameter, but Rx and Tx queue release callback use queue object which is used by Rx and Tx burst data plane callback. To align with other eth device queue configuration callbacks: - queue release callbacks are changed to use queue ID - all drivers are adapted Signed-off-by: Xueming Li <xuemingl@nvidia.com> Reviewed-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru> Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com> Acked-by: Somnath Kotur <somnath.kotur@broadcom.com> Acked-by: Ferruh Yigit <ferruh.yigit@intel.com>
82 lines
4.0 KiB
C
82 lines
4.0 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright (c) 2013-2015 Brocade Communications Systems, Inc.
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* Copyright (c) 2015-2018 Cavium Inc.
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* All rights reserved.
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* www.cavium.com
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*/
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#ifndef _BNX2X_RXTX_H_
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#define _BNX2X_RXTX_H_
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#define DEFAULT_TX_FREE_THRESH 64
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#define RTE_PMD_BNX2X_TX_MAX_BURST 1
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/**
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* Structure associated with each descriptor of the RX ring of a RX queue.
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*/
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struct bnx2x_rx_entry {
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struct rte_mbuf *mbuf; /**< mbuf associated with RX descriptor. */
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};
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/**
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* Structure associated with each RX queue.
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*/
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struct bnx2x_rx_queue {
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struct rte_mempool *mb_pool; /**< mbuf pool to populate RX ring. */
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union eth_rx_cqe *cq_ring; /**< RCQ ring virtual address. */
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uint64_t cq_ring_phys_addr; /**< RCQ ring DMA address. */
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uint64_t *rx_ring; /**< RX ring virtual address. */
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uint64_t rx_ring_phys_addr; /**< RX ring DMA address. */
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struct rte_mbuf **sw_ring; /**< address of RX software ring. */
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struct rte_mbuf *pkt_first_seg; /**< First segment of current packet. */
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struct rte_mbuf *pkt_last_seg; /**< Last segment of current packet. */
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uint16_t nb_cq_pages; /**< number of RCQ pages. */
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uint16_t nb_rx_desc; /**< number of RX descriptors. */
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uint16_t nb_rx_pages; /**< number of RX pages. */
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uint16_t rx_bd_head; /**< Index of current rx bd. */
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uint16_t rx_bd_tail; /**< Index of last rx bd. */
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uint16_t rx_cq_head; /**< Index of current rcq bd. */
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uint16_t rx_cq_tail; /**< Index of last rcq bd. */
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uint16_t queue_id; /**< RX queue index. */
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uint16_t port_id; /**< Device port identifier. */
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struct bnx2x_softc *sc; /**< Ptr to dev_private data. */
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};
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/**
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* Structure associated with each TX queue.
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*/
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struct bnx2x_tx_queue {
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/** TX ring virtual address. */
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union eth_tx_bd_types *tx_ring; /**< TX ring virtual address. */
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uint64_t tx_ring_phys_addr; /**< TX ring DMA address. */
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struct rte_mbuf **sw_ring; /**< virtual address of SW ring. */
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uint16_t tx_pkt_tail; /**< Index of current tx pkt. */
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uint16_t tx_pkt_head; /**< Index of last pkt counted by txeof. */
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uint16_t tx_bd_tail; /**< Index of current tx bd. */
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uint16_t tx_bd_head; /**< Index of last bd counted by txeof. */
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uint16_t nb_tx_desc; /**< number of TX descriptors. */
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uint16_t tx_free_thresh; /**< minimum TX before freeing. */
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uint16_t nb_tx_avail; /**< Number of TX descriptors available. */
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uint16_t nb_tx_pages; /**< number of TX pages */
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uint16_t queue_id; /**< TX queue index. */
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uint16_t port_id; /**< Device port identifier. */
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struct bnx2x_softc *sc; /**< Ptr to dev_private data */
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};
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int bnx2x_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id,
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uint16_t nb_rx_desc, unsigned int socket_id,
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const struct rte_eth_rxconf *rx_conf,
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struct rte_mempool *mb_pool);
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int bnx2x_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id,
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uint16_t nb_tx_desc, unsigned int socket_id,
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const struct rte_eth_txconf *tx_conf);
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void bnx2x_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t queue_idx);
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void bnx2x_dev_tx_queue_release(struct rte_eth_dev *dev, uint16_t queue_idx);
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void bnx2x_dev_rxtx_init(struct rte_eth_dev *dev);
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void bnx2x_dev_rxtx_init_dummy(struct rte_eth_dev *dev);
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void bnx2x_dev_clear_queues(struct rte_eth_dev *dev);
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#endif /* _BNX2X_RXTX_H_ */
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