0cb4150f82
Use latest firmware 7.13.11.
7.13.11 FW changelog:
- Packets from a VF with pvid configured which were sent with a
different vlan were transmitted instead of being discarded.
- In some multi-function configurations, inter-PF and inter-VF
Tx switching is incorrectly enabled.
- Wrong assert code in FLR final cleanup in case it is sent not
after FLR.
- Chip may stall in very rare cases under heavy traffic with FW GRO
enabled.
- VF malicious notification error fixes.
- Default gre tunnel to IPGRE which allows proper RSS for IPGRE
packets, L2GRE traffic will reach single queue.
- Removes unnecessary internal mem config, latest FW performs this
autonomously.
Update the PMD version to 1.1.0.1.
Signed-off-by: Rasesh Mody <rmody@marvell.com>
193 lines
7.0 KiB
C
193 lines
7.0 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright (c) 2007-2013 Broadcom Corporation.
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*
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* Eric Davis <edavis@broadcom.com>
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* David Christensen <davidch@broadcom.com>
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* Gary Zambrano <zambrano@broadcom.com>
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*
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* Copyright (c) 2014-2018 Cavium Inc.
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* All rights reserved.
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* www.cavium.com
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*/
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#ifndef ECORE_MFW_REQ_H
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#define ECORE_MFW_REQ_H
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#define PORT_0 0
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#define PORT_1 1
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#define PORT_MAX 2
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#define NVM_PATH_MAX 2
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/* FCoE capabilities required from the driver */
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struct fcoe_capabilities {
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uint32_t capability1;
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/* Maximum number of I/Os per connection */
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#define FCOE_IOS_PER_CONNECTION_MASK 0x0000ffff
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#define FCOE_IOS_PER_CONNECTION_SHIFT 0
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/* Maximum number of Logins per port */
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#define FCOE_LOGINS_PER_PORT_MASK 0xffff0000
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#define FCOE_LOGINS_PER_PORT_SHIFT 16
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uint32_t capability2;
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/* Maximum number of exchanges */
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#define FCOE_NUMBER_OF_EXCHANGES_MASK 0x0000ffff
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#define FCOE_NUMBER_OF_EXCHANGES_SHIFT 0
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/* Maximum NPIV WWN per port */
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#define FCOE_NPIV_WWN_PER_PORT_MASK 0xffff0000
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#define FCOE_NPIV_WWN_PER_PORT_SHIFT 16
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uint32_t capability3;
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/* Maximum number of targets supported */
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#define FCOE_TARGETS_SUPPORTED_MASK 0x0000ffff
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#define FCOE_TARGETS_SUPPORTED_SHIFT 0
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/* Maximum number of outstanding commands across all connections */
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#define FCOE_OUTSTANDING_COMMANDS_MASK 0xffff0000
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#define FCOE_OUTSTANDING_COMMANDS_SHIFT 16
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uint32_t capability4;
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#define FCOE_CAPABILITY4_STATEFUL 0x00000001
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#define FCOE_CAPABILITY4_STATELESS 0x00000002
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#define FCOE_CAPABILITY4_CAPABILITIES_REPORTED_VALID 0x00000004
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};
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struct glob_ncsi_oem_data
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{
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uint32_t driver_version;
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uint32_t unused[3];
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struct fcoe_capabilities fcoe_features[NVM_PATH_MAX][PORT_MAX];
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};
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/* current drv_info version */
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#define DRV_INFO_CUR_VER 2
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/* drv_info op codes supported */
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enum drv_info_opcode {
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ETH_STATS_OPCODE,
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FCOE_STATS_OPCODE,
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ISCSI_STATS_OPCODE
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};
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#define ETH_STAT_INFO_VERSION_LEN 12
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/* Per PCI Function Ethernet Statistics required from the driver */
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struct eth_stats_info {
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/* Function's Driver Version. padded to 12 */
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char version[ETH_STAT_INFO_VERSION_LEN];
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/* Locally Admin Addr. BigEndian EIU48. Actual size is 6 bytes */
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uint8_t mac_local[8];
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uint8_t mac_add1[8]; /* Additional Programmed MAC Addr 1. */
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uint8_t mac_add2[8]; /* Additional Programmed MAC Addr 2. */
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uint32_t mtu_size; /* MTU Size. Note : Negotiated MTU */
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uint32_t feature_flags; /* Feature_Flags. */
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#define FEATURE_ETH_CHKSUM_OFFLOAD_MASK 0x01
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#define FEATURE_ETH_LSO_MASK 0x02
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#define FEATURE_ETH_BOOTMODE_MASK 0x1C
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#define FEATURE_ETH_BOOTMODE_SHIFT 2
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#define FEATURE_ETH_BOOTMODE_NONE (0x0 << 2)
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#define FEATURE_ETH_BOOTMODE_PXE (0x1 << 2)
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#define FEATURE_ETH_BOOTMODE_ISCSI (0x2 << 2)
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#define FEATURE_ETH_BOOTMODE_FCOE (0x3 << 2)
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#define FEATURE_ETH_TOE_MASK 0x20
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uint32_t lso_max_size; /* LSO MaxOffloadSize. */
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uint32_t lso_min_seg_cnt; /* LSO MinSegmentCount. */
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/* Num Offloaded Connections TCP_IPv4. */
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uint32_t ipv4_ofld_cnt;
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/* Num Offloaded Connections TCP_IPv6. */
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uint32_t ipv6_ofld_cnt;
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uint32_t promiscuous_mode; /* Promiscuous Mode. non-zero true */
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uint32_t txq_size; /* TX Descriptors Queue Size */
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uint32_t rxq_size; /* RX Descriptors Queue Size */
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/* TX Descriptor Queue Avg Depth. % Avg Queue Depth since last poll */
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uint32_t txq_avg_depth;
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/* RX Descriptors Queue Avg Depth. % Avg Queue Depth since last poll */
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uint32_t rxq_avg_depth;
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/* IOV_Offload. 0=none; 1=MultiQueue, 2=VEB 3= VEPA*/
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uint32_t iov_offload;
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/* Number of NetQueue/VMQ Config'd. */
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uint32_t netq_cnt;
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uint32_t vf_cnt; /* Num VF assigned to this PF. */
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};
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/* Per PCI Function FCOE Statistics required from the driver */
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struct fcoe_stats_info {
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uint8_t version[12]; /* Function's Driver Version. */
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uint8_t mac_local[8]; /* Locally Admin Addr. */
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uint8_t mac_add1[8]; /* Additional Programmed MAC Addr 1. */
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uint8_t mac_add2[8]; /* Additional Programmed MAC Addr 2. */
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/* QoS Priority (per 802.1p). 0-7255 */
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uint32_t qos_priority;
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uint32_t txq_size; /* FCoE TX Descriptors Queue Size. */
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uint32_t rxq_size; /* FCoE RX Descriptors Queue Size. */
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/* FCoE TX Descriptor Queue Avg Depth. */
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uint32_t txq_avg_depth;
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/* FCoE RX Descriptors Queue Avg Depth. */
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uint32_t rxq_avg_depth;
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uint32_t rx_frames_lo; /* FCoE RX Frames received. */
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uint32_t rx_frames_hi; /* FCoE RX Frames received. */
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uint32_t rx_bytes_lo; /* FCoE RX Bytes received. */
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uint32_t rx_bytes_hi; /* FCoE RX Bytes received. */
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uint32_t tx_frames_lo; /* FCoE TX Frames sent. */
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uint32_t tx_frames_hi; /* FCoE TX Frames sent. */
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uint32_t tx_bytes_lo; /* FCoE TX Bytes sent. */
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uint32_t tx_bytes_hi; /* FCoE TX Bytes sent. */
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uint32_t rx_fcs_errors; /* number of receive packets with FCS errors */
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uint32_t rx_fc_crc_errors; /* number of FC frames with CRC errors*/
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uint32_t fip_login_failures; /* number of FCoE/FIP Login failures */
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};
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/* Per PCI Function iSCSI Statistics required from the driver*/
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struct iscsi_stats_info {
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uint8_t version[12]; /* Function's Driver Version. */
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uint8_t mac_local[8]; /* Locally Admin iSCSI MAC Addr. */
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uint8_t mac_add1[8]; /* Additional Programmed MAC Addr 1. */
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/* QoS Priority (per 802.1p). 0-7255 */
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uint32_t qos_priority;
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#define ISCSI_QOS_PRIORITY_OFFSET 0
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#define ISCSI_QOS_PRIORITY_MASK (0xffff)
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#define ISCSI_IP_ADDRESS_TYPE_OFFSET 30
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#define ISCSI_IP_ADDRESS_TYPE_MASK (3 << 30)
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/* Driver does not have the IP address and type populated */
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#define ISCSI_IP_ADDRESS_TYPE_NOT_SET (0 << 30)
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#define ISCSI_IP_ADDRESS_TYPE_IPV4 (1 << 30) /* IPV4 IP address set */
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#define ISCSI_IP_ADDRESS_TYPE_IPV6 (2 << 30) /* IPV6 IP address set */
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uint8_t initiator_name[64]; /* iSCSI Boot Initiator Node name. */
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uint8_t ww_port_name[64]; /* iSCSI World wide port name */
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uint8_t boot_target_name[64];/* iSCSI Boot Target Name. */
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uint8_t boot_target_ip[16]; /* iSCSI Boot Target IP. */
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uint32_t boot_target_portal; /* iSCSI Boot Target Portal. */
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uint8_t boot_init_ip[16]; /* iSCSI Boot Initiator IP Address. */
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uint32_t max_frame_size; /* Max Frame Size. bytes */
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uint32_t txq_size; /* PDU TX Descriptors Queue Size. */
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uint32_t rxq_size; /* PDU RX Descriptors Queue Size. */
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uint32_t txq_avg_depth; /*PDU TX Descriptor Queue Avg Depth. */
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uint32_t rxq_avg_depth; /*PDU RX Descriptors Queue Avg Depth. */
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uint32_t rx_pdus_lo; /* iSCSI PDUs received. */
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uint32_t rx_pdus_hi; /* iSCSI PDUs received. */
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uint32_t rx_bytes_lo; /* iSCSI RX Bytes received. */
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uint32_t rx_bytes_hi; /* iSCSI RX Bytes received. */
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uint32_t tx_pdus_lo; /* iSCSI PDUs sent. */
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uint32_t tx_pdus_hi; /* iSCSI PDUs sent. */
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uint32_t tx_bytes_lo; /* iSCSI PDU TX Bytes sent. */
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uint32_t tx_bytes_hi; /* iSCSI PDU TX Bytes sent. */
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uint32_t pcp_prior_map_tbl; /*C-PCP to S-PCP Priority MapTable.
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9 nibbles, the position of each nibble
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represents the C-PCP value, the value
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of the nibble = S-PCP value.*/
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};
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union drv_info_to_mcp {
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struct eth_stats_info ether_stat;
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struct fcoe_stats_info fcoe_stat;
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struct iscsi_stats_info iscsi_stat;
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};
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#endif /* ECORE_MFW_REQ_H */
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