Alex Marginean d84612e9bd net/enetc: init SI transactions attribute register ... This was left to its default value. With the patch transactions are: - coherent, - do not allocate in downstream cache (there is none on LS1028a), - merge surrounding data for BD writes, - overwrite surrounding data for frame data writes. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Acked-by: Gagandeep Singh <g.singh@nxp.com>		2020-03-18 10:21:41 +01:00
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enetc_hw.h	net/enetc: init SI transactions attribute register	2020-03-18 10:21:41 +01:00