25cf263074
Multiple drivers are defining macros for VLAN header length, to remove the redundancy defining macro in the ether header. And updated drivers to use the new macro. Signed-off-by: Ferruh Yigit <ferruh.yigit@intel.com> Acked-by: Haiyue Wang <haiyue.wang@intel.com> Acked-by: Rosen Xu <rosen.xu@intel.com> Acked-by: Jiawen Wu <jiawenwu@trustnetic.com>
153 lines
3.5 KiB
C
153 lines
3.5 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright 2020-2021 NXP
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*/
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#ifndef __ENETFEC_ETHDEV_H__
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#define __ENETFEC_ETHDEV_H__
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#include <rte_ethdev.h>
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#define BD_LEN 49152
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#define ENETFEC_TX_FR_SIZE 2048
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#define ETH_HLEN RTE_ETHER_HDR_LEN
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/* full duplex */
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#define FULL_DUPLEX 0x00
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#define MAX_TX_BD_RING_SIZE 512 /* It should be power of 2 */
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#define MAX_RX_BD_RING_SIZE 512
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#define PKT_MAX_BUF_SIZE 1984
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#define OPT_FRAME_SIZE (PKT_MAX_BUF_SIZE << 16)
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#define ENETFEC_MAX_RX_PKT_LEN 3000
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#define __iomem
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#if defined(RTE_ARCH_ARM)
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#if defined(RTE_ARCH_64)
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#define dcbf(p) { asm volatile("dc cvac, %0" : : "r"(p) : "memory"); }
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#define dcbf_64(p) dcbf(p)
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#else /* RTE_ARCH_32 */
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#define dcbf(p) RTE_SET_USED(p)
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#define dcbf_64(p) dcbf(p)
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#endif
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#else
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#define dcbf(p) RTE_SET_USED(p)
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#define dcbf_64(p) dcbf(p)
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#endif
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/*
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* ENETFEC can support 1 rx and tx queue..
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*/
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#define ENETFEC_MAX_Q 1
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#define writel(v, p) ({*(volatile unsigned int *)(p) = (v); })
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#define readl(p) rte_read32(p)
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struct bufdesc {
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uint16_t bd_datlen; /* buffer data length */
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uint16_t bd_sc; /* buffer control & status */
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uint32_t bd_bufaddr; /* buffer address */
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};
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struct bufdesc_ex {
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struct bufdesc desc;
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uint32_t bd_esc;
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uint32_t bd_prot;
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uint32_t bd_bdu;
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uint32_t ts;
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uint16_t res0[4];
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};
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struct bufdesc_prop {
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int queue_id;
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/* Addresses of Tx and Rx buffers */
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struct bufdesc *base;
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struct bufdesc *last;
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struct bufdesc *cur;
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void __iomem *active_reg_desc;
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uint64_t descr_baseaddr_p;
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unsigned short ring_size;
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unsigned char d_size;
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unsigned char d_size_log2;
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};
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struct enetfec_priv_tx_q {
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struct bufdesc_prop bd;
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struct rte_mbuf *tx_mbuf[MAX_TX_BD_RING_SIZE];
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struct bufdesc *dirty_tx;
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struct rte_mempool *pool;
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struct enetfec_private *fep;
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};
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struct enetfec_priv_rx_q {
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struct bufdesc_prop bd;
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struct rte_mbuf *rx_mbuf[MAX_RX_BD_RING_SIZE];
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struct rte_mempool *pool;
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struct enetfec_private *fep;
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};
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struct enetfec_private {
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struct rte_eth_dev *dev;
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struct rte_eth_stats stats;
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int full_duplex;
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int flag_pause;
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int flag_csum;
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uint32_t quirks;
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uint32_t cbus_size;
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uint32_t enetfec_e_cntl;
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uint16_t max_rx_queues;
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uint16_t max_tx_queues;
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unsigned int total_tx_ring_size;
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unsigned int total_rx_ring_size;
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unsigned int reg_size;
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unsigned int bd_size;
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bool bufdesc_ex;
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bool rgmii_txc_delay;
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bool rgmii_rxc_delay;
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void *hw_baseaddr_v;
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void *bd_addr_v;
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uint32_t hw_baseaddr_p;
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uint32_t bd_addr_p;
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uint32_t bd_addr_p_r[ENETFEC_MAX_Q];
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uint32_t bd_addr_p_t[ENETFEC_MAX_Q];
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void *dma_baseaddr_r[ENETFEC_MAX_Q];
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void *dma_baseaddr_t[ENETFEC_MAX_Q];
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struct enetfec_priv_rx_q *rx_queues[ENETFEC_MAX_Q];
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struct enetfec_priv_tx_q *tx_queues[ENETFEC_MAX_Q];
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};
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static inline struct
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bufdesc *enet_get_nextdesc(struct bufdesc *bdp, struct bufdesc_prop *bd)
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{
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return (bdp >= bd->last) ? bd->base
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: (struct bufdesc *)(((uintptr_t)bdp) + bd->d_size);
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}
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static inline int
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fls64(unsigned long word)
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{
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return (64 - __builtin_clzl(word)) - 1;
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}
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static inline struct
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bufdesc *enet_get_prevdesc(struct bufdesc *bdp, struct bufdesc_prop *bd)
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{
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return (bdp <= bd->base) ? bd->last
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: (struct bufdesc *)(((uintptr_t)bdp) - bd->d_size);
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}
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static inline int
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enet_get_bd_index(struct bufdesc *bdp, struct bufdesc_prop *bd)
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{
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return ((const char *)bdp - (const char *)bd->base) >> bd->d_size_log2;
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}
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uint16_t enetfec_recv_pkts(void *rxq1, struct rte_mbuf **rx_pkts,
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uint16_t nb_pkts);
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uint16_t enetfec_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
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uint16_t nb_pkts);
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#endif /*__ENETFEC_ETHDEV_H__*/
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