b0290e56dd
Context is the first mlx5dr object created, all sub objects table, matcher, rule, and action are created using the context. The context holds the capabilities and the send queues used for configuring the offloads to the HW. Signed-off-by: Alex Vesker <valex@nvidia.com>
41 lines
1.1 KiB
C
41 lines
1.1 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright (c) 2022 NVIDIA Corporation & Affiliates
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*/
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#ifndef MLX5DR_CONTEXT_H_
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#define MLX5DR_CONTEXT_H_
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enum mlx5dr_context_flags {
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MLX5DR_CONTEXT_FLAG_HWS_SUPPORT = 1 << 0,
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MLX5DR_CONTEXT_FLAG_PRIVATE_PD = 1 << 1,
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};
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enum mlx5dr_context_shared_stc_type {
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MLX5DR_CONTEXT_SHARED_STC_DECAP = 0,
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MLX5DR_CONTEXT_SHARED_STC_POP = 1,
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MLX5DR_CONTEXT_SHARED_STC_MAX = 2,
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};
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struct mlx5dr_context_common_res {
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struct mlx5dr_action_default_stc *default_stc;
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struct mlx5dr_action_shared_stc *shared_stc[MLX5DR_CONTEXT_SHARED_STC_MAX];
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struct mlx5dr_cmd_forward_tbl *default_miss;
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};
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struct mlx5dr_context {
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struct ibv_context *ibv_ctx;
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struct mlx5dr_cmd_query_caps *caps;
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struct ibv_pd *pd;
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uint32_t pd_num;
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struct mlx5dr_pool *stc_pool[MLX5DR_TABLE_TYPE_MAX];
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struct mlx5dr_context_common_res common_res[MLX5DR_TABLE_TYPE_MAX];
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struct mlx5dr_pattern_cache *pattern_cache;
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pthread_spinlock_t ctrl_lock;
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enum mlx5dr_context_flags flags;
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struct mlx5dr_send_engine *send_queue;
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size_t queues;
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LIST_HEAD(table_head, mlx5dr_table) head;
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};
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#endif /* MLX5DR_CONTEXT_H_ */
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