04a4de756e
Add support for AGE action for HW steering. This patch includes: 1. Add new structures to manage aging. 2. Initialize all of them in configure function. 3. Implement per second aging check using CNT background thread. 4. Enable AGE action in flow create/destroy operations. 5. Implement a queue-based function to report aged flow rules. Signed-off-by: Michael Baum <michaelba@nvidia.com> Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
674 lines
19 KiB
C
674 lines
19 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright 2015 6WIND S.A.
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* Copyright 2015 Mellanox Technologies, Ltd
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*/
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#ifndef RTE_PMD_MLX5_UTILS_H_
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#define RTE_PMD_MLX5_UTILS_H_
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#include <stddef.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <limits.h>
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#include <errno.h>
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#include <rte_spinlock.h>
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#include <rte_rwlock.h>
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#include <rte_memory.h>
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#include <rte_bitmap.h>
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#include <mlx5_common.h>
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#include <mlx5_common_utils.h>
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#include "mlx5_defs.h"
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/* Convert a bit number to the corresponding 64-bit mask */
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#define MLX5_BITSHIFT(v) (UINT64_C(1) << (v))
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/* Save and restore errno around argument evaluation. */
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#define ERRNO_SAFE(x) ((errno = (int []){ errno, ((x), 0) }[0]))
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extern int mlx5_logtype;
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#define MLX5_NET_LOG_PREFIX "mlx5_net"
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/* Generic printf()-like logging macro with automatic line feed. */
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#define DRV_LOG(level, ...) \
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PMD_DRV_LOG_(level, mlx5_logtype, MLX5_NET_LOG_PREFIX, \
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__VA_ARGS__ PMD_DRV_LOG_STRIP PMD_DRV_LOG_OPAREN, \
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PMD_DRV_LOG_CPAREN)
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/* Convenience macros for accessing mbuf fields. */
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#define NEXT(m) ((m)->next)
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#define DATA_LEN(m) ((m)->data_len)
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#define PKT_LEN(m) ((m)->pkt_len)
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#define DATA_OFF(m) ((m)->data_off)
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#define SET_DATA_OFF(m, o) ((m)->data_off = (o))
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#define NB_SEGS(m) ((m)->nb_segs)
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#define PORT(m) ((m)->port)
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/* Transpose flags. Useful to convert IBV to DPDK flags. */
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#define TRANSPOSE(val, from, to) \
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(((from) >= (to)) ? \
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(((val) & (from)) / ((from) / (to))) : \
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(((val) & (from)) * ((to) / (from))))
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/*
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* For the case which data is linked with sequence increased index, the
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* array table will be more efficient than hash table once need to search
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* one data entry in large numbers of entries. Since the traditional hash
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* tables has fixed table size, when huge numbers of data saved to the hash
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* table, it also comes lots of hash conflict.
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*
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* But simple array table also has fixed size, allocates all the needed
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* memory at once will waste lots of memory. For the case don't know the
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* exactly number of entries will be impossible to allocate the array.
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*
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* Then the multiple level table helps to balance the two disadvantages.
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* Allocate a global high level table with sub table entries at first,
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* the global table contains the sub table entries, and the sub table will
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* be allocated only once the corresponding index entry need to be saved.
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* e.g. for up to 32-bits index, three level table with 10-10-12 splitting,
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* with sequence increased index, the memory grows with every 4K entries.
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*
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* The currently implementation introduces 10-10-12 32-bits splitting
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* Three-Level table to help the cases which have millions of enties to
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* save. The index entries can be addressed directly by the index, no
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* search will be needed.q
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*/
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/* L3 table global table define. */
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#define MLX5_L3T_GT_OFFSET 22
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#define MLX5_L3T_GT_SIZE (1 << 10)
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#define MLX5_L3T_GT_MASK (MLX5_L3T_GT_SIZE - 1)
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/* L3 table middle table define. */
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#define MLX5_L3T_MT_OFFSET 12
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#define MLX5_L3T_MT_SIZE (1 << 10)
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#define MLX5_L3T_MT_MASK (MLX5_L3T_MT_SIZE - 1)
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/* L3 table entry table define. */
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#define MLX5_L3T_ET_OFFSET 0
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#define MLX5_L3T_ET_SIZE (1 << 12)
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#define MLX5_L3T_ET_MASK (MLX5_L3T_ET_SIZE - 1)
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/* L3 table type. */
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enum mlx5_l3t_type {
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MLX5_L3T_TYPE_WORD = 0,
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MLX5_L3T_TYPE_DWORD,
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MLX5_L3T_TYPE_QWORD,
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MLX5_L3T_TYPE_PTR,
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MLX5_L3T_TYPE_MAX,
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};
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struct mlx5_indexed_pool;
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/* Generic data struct. */
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union mlx5_l3t_data {
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uint16_t word;
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uint32_t dword;
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uint64_t qword;
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void *ptr;
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};
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/* L3 level table data structure. */
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struct mlx5_l3t_level_tbl {
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uint64_t ref_cnt; /* Table ref_cnt. */
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void *tbl[]; /* Table array. */
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};
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/* L3 word entry table data structure. */
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struct mlx5_l3t_entry_word {
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uint32_t idx; /* Table index. */
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uint64_t ref_cnt; /* Table ref_cnt. */
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struct {
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uint16_t data;
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uint32_t ref_cnt;
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} entry[MLX5_L3T_ET_SIZE]; /* Entry array */
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} __rte_packed;
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/* L3 double word entry table data structure. */
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struct mlx5_l3t_entry_dword {
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uint32_t idx; /* Table index. */
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uint64_t ref_cnt; /* Table ref_cnt. */
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struct {
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uint32_t data;
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int32_t ref_cnt;
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} entry[MLX5_L3T_ET_SIZE]; /* Entry array */
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} __rte_packed;
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/* L3 quad word entry table data structure. */
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struct mlx5_l3t_entry_qword {
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uint32_t idx; /* Table index. */
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uint64_t ref_cnt; /* Table ref_cnt. */
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struct {
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uint64_t data;
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uint32_t ref_cnt;
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} entry[MLX5_L3T_ET_SIZE]; /* Entry array */
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} __rte_packed;
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/* L3 pointer entry table data structure. */
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struct mlx5_l3t_entry_ptr {
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uint32_t idx; /* Table index. */
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uint64_t ref_cnt; /* Table ref_cnt. */
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struct {
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void *data;
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uint32_t ref_cnt;
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} entry[MLX5_L3T_ET_SIZE]; /* Entry array */
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} __rte_packed;
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/* L3 table data structure. */
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struct mlx5_l3t_tbl {
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enum mlx5_l3t_type type; /* Table type. */
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struct mlx5_indexed_pool *eip;
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/* Table index pool handles. */
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struct mlx5_l3t_level_tbl *tbl; /* Global table index. */
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rte_spinlock_t sl; /* The table lock. */
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};
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/** Type of function that is used to handle the data before freeing. */
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typedef int32_t (*mlx5_l3t_alloc_callback_fn)(void *ctx,
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union mlx5_l3t_data *data);
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/*
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* The default ipool threshold value indicates which per_core_cache
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* value to set.
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*/
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#define MLX5_HW_IPOOL_SIZE_THRESHOLD (1 << 19)
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/* The default min local cache size. */
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#define MLX5_HW_IPOOL_CACHE_MIN (1 << 9)
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/*
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* The indexed memory entry index is made up of trunk index and offset of
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* the entry in the trunk. Since the entry index is 32 bits, in case user
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* prefers to have small trunks, user can change the macro below to a big
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* number which helps the pool contains more trunks with lots of entries
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* allocated.
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*/
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#define TRUNK_IDX_BITS 16
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#define TRUNK_MAX_IDX ((1 << TRUNK_IDX_BITS) - 1)
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#define TRUNK_INVALID TRUNK_MAX_IDX
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#define MLX5_IPOOL_DEFAULT_TRUNK_SIZE (1 << (28 - TRUNK_IDX_BITS))
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#ifdef RTE_LIBRTE_MLX5_DEBUG
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#define POOL_DEBUG 1
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#endif
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struct mlx5_indexed_pool_config {
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uint32_t size; /* Pool entry size. */
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uint32_t trunk_size:22;
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/*
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* Trunk entry number. Must be power of 2. It can be increased
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* if trunk_grow enable. The trunk entry number increases with
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* left shift grow_shift. Trunks with index are after grow_trunk
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* will keep the entry number same with the last grow trunk.
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*/
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uint32_t grow_trunk:4;
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/*
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* Trunks with entry number increase in the pool. Set it to 0
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* to make the pool works as trunk entry fixed pool. It works
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* only if grow_shift is not 0.
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*/
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uint32_t grow_shift:4;
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/*
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* Trunk entry number increase shift value, stop after grow_trunk.
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* It works only if grow_trunk is not 0.
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*/
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uint32_t need_lock:1;
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/* Lock is needed for multiple thread usage. */
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uint32_t release_mem_en:1; /* Release trunk when it is free. */
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uint32_t max_idx; /* The maximum index can be allocated. */
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uint32_t per_core_cache;
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/*
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* Cache entry number per core for performance. Should not be
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* set with release_mem_en.
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*/
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const char *type; /* Memory allocate type name. */
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void *(*malloc)(uint32_t flags, size_t size, unsigned int align,
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int socket);
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/* User defined memory allocator. */
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void (*free)(void *addr); /* User defined memory release. */
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};
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struct mlx5_indexed_trunk {
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uint32_t idx; /* Trunk id. */
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uint32_t prev; /* Previous free trunk in free list. */
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uint32_t next; /* Next free trunk in free list. */
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uint32_t free; /* Free entries available */
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struct rte_bitmap *bmp;
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uint8_t data[] __rte_cache_aligned; /* Entry data start. */
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};
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struct mlx5_indexed_cache {
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struct mlx5_indexed_trunk **trunks;
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volatile uint32_t n_trunk_valid; /* Trunks allocated. */
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uint32_t n_trunk; /* Trunk pointer array size. */
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uint32_t ref_cnt;
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uint32_t len;
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uint32_t idx[];
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};
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struct mlx5_ipool_per_lcore {
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struct mlx5_indexed_cache *lc;
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uint32_t len; /**< Current cache count. */
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uint32_t idx[]; /**< Cache objects. */
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};
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struct mlx5_indexed_pool {
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struct mlx5_indexed_pool_config cfg; /* Indexed pool configuration. */
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rte_spinlock_t rsz_lock; /* Pool lock for multiple thread usage. */
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rte_spinlock_t lcore_lock;
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/* Dim of trunk pointer array. */
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union {
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struct {
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uint32_t n_trunk_valid; /* Trunks allocated. */
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uint32_t n_trunk; /* Trunk pointer array size. */
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struct mlx5_indexed_trunk **trunks;
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uint32_t free_list; /* Index to first free trunk. */
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};
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struct {
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struct mlx5_indexed_cache *gc;
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/* Global cache. */
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struct mlx5_ipool_per_lcore *cache[RTE_MAX_LCORE + 1];
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/* Local cache. */
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struct rte_bitmap *ibmp;
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void *bmp_mem;
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/* Allocate objects bitmap. Use during flush. */
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};
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};
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#ifdef POOL_DEBUG
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uint32_t n_entry;
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uint32_t trunk_new;
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uint32_t trunk_avail;
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uint32_t trunk_empty;
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uint32_t trunk_free;
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#endif
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uint32_t grow_tbl[]; /* Save the index offset for the grow trunks. */
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};
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/**
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* Return logarithm of the nearest power of two above input value.
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*
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* @param v
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* Input value.
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*
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* @return
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* Logarithm of the nearest power of two above input value.
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*/
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static inline unsigned int
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log2above(unsigned int v)
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{
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unsigned int l;
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unsigned int r;
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for (l = 0, r = 0; (v >> 1); ++l, v >>= 1)
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r |= (v & 1);
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return l + r;
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}
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/********************************* indexed pool *************************/
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/**
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* This function allocates non-initialized memory entry from pool.
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* In NUMA systems, the memory entry allocated resides on the same
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* NUMA socket as the core that calls this function.
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*
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* Memory entry is allocated from memory trunk, no alignment.
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*
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* @param pool
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* Pointer to indexed memory entry pool.
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* No initialization required.
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* @param[out] idx
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* Pointer to memory to save allocated index.
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* Memory index always positive value.
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* @return
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* - Pointer to the allocated memory entry.
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* - NULL on error. Not enough memory, or invalid arguments.
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*/
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void *mlx5_ipool_malloc(struct mlx5_indexed_pool *pool, uint32_t *idx);
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/**
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* This function allocates zero initialized memory entry from pool.
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* In NUMA systems, the memory entry allocated resides on the same
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* NUMA socket as the core that calls this function.
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*
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* Memory entry is allocated from memory trunk, no alignment.
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*
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* @param pool
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* Pointer to indexed memory pool.
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* No initialization required.
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* @param[out] idx
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* Pointer to memory to save allocated index.
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* Memory index always positive value.
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* @return
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* - Pointer to the allocated memory entry .
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* - NULL on error. Not enough memory, or invalid arguments.
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*/
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void *mlx5_ipool_zmalloc(struct mlx5_indexed_pool *pool, uint32_t *idx);
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/**
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* This function frees indexed memory entry to pool.
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* Caller has to make sure that the index is allocated from same pool.
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*
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* @param pool
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* Pointer to indexed memory pool.
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* @param idx
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* Allocated memory entry index.
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*/
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void mlx5_ipool_free(struct mlx5_indexed_pool *pool, uint32_t idx);
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/**
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* This function returns pointer of indexed memory entry from index.
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* Caller has to make sure that the index is valid, and allocated
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* from same pool.
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*
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* @param pool
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* Pointer to indexed memory pool.
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* @param idx
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* Allocated memory index.
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* @return
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* - Pointer to indexed memory entry.
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*/
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void *mlx5_ipool_get(struct mlx5_indexed_pool *pool, uint32_t idx);
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/**
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* This function creates indexed memory pool.
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* Caller has to configure the configuration accordingly.
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*
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* @param pool
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* Pointer to indexed memory pool.
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* @param cfg
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* Allocated memory index.
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*/
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struct mlx5_indexed_pool *
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mlx5_ipool_create(struct mlx5_indexed_pool_config *cfg);
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/**
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* This function releases all resources of pool.
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* Caller has to make sure that all indexes and memories allocated
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* from this pool not referenced anymore.
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*
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* @param pool
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* Pointer to indexed memory pool.
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* @return
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* - non-zero value on error.
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* - 0 on success.
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*/
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int mlx5_ipool_destroy(struct mlx5_indexed_pool *pool);
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/**
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* This function dumps debug info of pool.
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*
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* @param pool
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* Pointer to indexed memory pool.
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*/
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void mlx5_ipool_dump(struct mlx5_indexed_pool *pool);
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/**
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* This function flushes all the cache index back to pool trunk.
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*
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* @param pool
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* Pointer to the index memory pool handler.
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*
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*/
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void mlx5_ipool_flush_cache(struct mlx5_indexed_pool *pool);
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/**
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* This function gets the available entry from pos.
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*
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* @param pool
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* Pointer to the index memory pool handler.
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* @param pos
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* Pointer to the index position start from.
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*
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* @return
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* - Pointer to the next available entry.
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*
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*/
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void *mlx5_ipool_get_next(struct mlx5_indexed_pool *pool, uint32_t *pos);
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/**
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* This function allocates new empty Three-level table.
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*
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* @param type
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* The l3t can set as word, double word, quad word or pointer with index.
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*
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* @return
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* - Pointer to the allocated l3t.
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* - NULL on error. Not enough memory, or invalid arguments.
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*/
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struct mlx5_l3t_tbl *mlx5_l3t_create(enum mlx5_l3t_type type);
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/**
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* This function destroys Three-level table.
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*
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* @param tbl
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* Pointer to the l3t.
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*/
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void mlx5_l3t_destroy(struct mlx5_l3t_tbl *tbl);
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/**
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* This function gets the index entry from Three-level table.
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*
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* @param tbl
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* Pointer to the l3t.
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* @param idx
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* Index to the entry.
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* @param data
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* Pointer to the memory which saves the entry data.
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* When function call returns 0, data contains the entry data get from
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* l3t.
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* When function call returns -1, data is not modified.
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*
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* @return
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* 0 if success, -1 on error.
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*/
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int32_t mlx5_l3t_get_entry(struct mlx5_l3t_tbl *tbl, uint32_t idx,
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union mlx5_l3t_data *data);
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/**
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* This function decreases and clear index entry if reference
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* counter is 0 from Three-level table.
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*
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* @param tbl
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* Pointer to the l3t.
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* @param idx
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* Index to the entry.
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*
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* @return
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* The remaining reference count, 0 means entry be cleared, -1 on error.
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*/
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int32_t mlx5_l3t_clear_entry(struct mlx5_l3t_tbl *tbl, uint32_t idx);
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/**
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* This function sets the index entry to Three-level table.
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* If the entry is already set, the EEXIST errno will be given, and
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* the set data will be filled to the data.
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*
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* @param tbl[in]
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* Pointer to the l3t.
|
|
* @param idx[in]
|
|
* Index to the entry.
|
|
* @param data[in/out]
|
|
* Pointer to the memory which contains the entry data save to l3t.
|
|
* If the entry is already set, the set data will be filled.
|
|
*
|
|
* @return
|
|
* 0 if success, -1 on error.
|
|
*/
|
|
int32_t mlx5_l3t_set_entry(struct mlx5_l3t_tbl *tbl, uint32_t idx,
|
|
union mlx5_l3t_data *data);
|
|
|
|
static inline void *
|
|
mlx5_l3t_get_next(struct mlx5_l3t_tbl *tbl, uint32_t *pos)
|
|
{
|
|
struct mlx5_l3t_level_tbl *g_tbl, *m_tbl;
|
|
uint32_t i, j, k, g_start, m_start, e_start;
|
|
uint32_t idx = *pos;
|
|
void *e_tbl;
|
|
struct mlx5_l3t_entry_word *w_e_tbl;
|
|
struct mlx5_l3t_entry_dword *dw_e_tbl;
|
|
struct mlx5_l3t_entry_qword *qw_e_tbl;
|
|
struct mlx5_l3t_entry_ptr *ptr_e_tbl;
|
|
|
|
if (!tbl)
|
|
return NULL;
|
|
g_tbl = tbl->tbl;
|
|
if (!g_tbl)
|
|
return NULL;
|
|
g_start = (idx >> MLX5_L3T_GT_OFFSET) & MLX5_L3T_GT_MASK;
|
|
m_start = (idx >> MLX5_L3T_MT_OFFSET) & MLX5_L3T_MT_MASK;
|
|
e_start = idx & MLX5_L3T_ET_MASK;
|
|
for (i = g_start; i < MLX5_L3T_GT_SIZE; i++) {
|
|
m_tbl = g_tbl->tbl[i];
|
|
if (!m_tbl) {
|
|
/* Jump to new table, reset the sub table start. */
|
|
m_start = 0;
|
|
e_start = 0;
|
|
continue;
|
|
}
|
|
for (j = m_start; j < MLX5_L3T_MT_SIZE; j++) {
|
|
if (!m_tbl->tbl[j]) {
|
|
/*
|
|
* Jump to new table, reset the sub table
|
|
* start.
|
|
*/
|
|
e_start = 0;
|
|
continue;
|
|
}
|
|
e_tbl = m_tbl->tbl[j];
|
|
switch (tbl->type) {
|
|
case MLX5_L3T_TYPE_WORD:
|
|
w_e_tbl = (struct mlx5_l3t_entry_word *)e_tbl;
|
|
for (k = e_start; k < MLX5_L3T_ET_SIZE; k++) {
|
|
if (!w_e_tbl->entry[k].data)
|
|
continue;
|
|
*pos = (i << MLX5_L3T_GT_OFFSET) |
|
|
(j << MLX5_L3T_MT_OFFSET) | k;
|
|
return (void *)&w_e_tbl->entry[k].data;
|
|
}
|
|
break;
|
|
case MLX5_L3T_TYPE_DWORD:
|
|
dw_e_tbl = (struct mlx5_l3t_entry_dword *)e_tbl;
|
|
for (k = e_start; k < MLX5_L3T_ET_SIZE; k++) {
|
|
if (!dw_e_tbl->entry[k].data)
|
|
continue;
|
|
*pos = (i << MLX5_L3T_GT_OFFSET) |
|
|
(j << MLX5_L3T_MT_OFFSET) | k;
|
|
return (void *)&dw_e_tbl->entry[k].data;
|
|
}
|
|
break;
|
|
case MLX5_L3T_TYPE_QWORD:
|
|
qw_e_tbl = (struct mlx5_l3t_entry_qword *)e_tbl;
|
|
for (k = e_start; k < MLX5_L3T_ET_SIZE; k++) {
|
|
if (!qw_e_tbl->entry[k].data)
|
|
continue;
|
|
*pos = (i << MLX5_L3T_GT_OFFSET) |
|
|
(j << MLX5_L3T_MT_OFFSET) | k;
|
|
return (void *)&qw_e_tbl->entry[k].data;
|
|
}
|
|
break;
|
|
default:
|
|
ptr_e_tbl = (struct mlx5_l3t_entry_ptr *)e_tbl;
|
|
for (k = e_start; k < MLX5_L3T_ET_SIZE; k++) {
|
|
if (!ptr_e_tbl->entry[k].data)
|
|
continue;
|
|
*pos = (i << MLX5_L3T_GT_OFFSET) |
|
|
(j << MLX5_L3T_MT_OFFSET) | k;
|
|
return ptr_e_tbl->entry[k].data;
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
return NULL;
|
|
}
|
|
|
|
/*
|
|
* Macros for linked list based on indexed memory.
|
|
* Example data structure:
|
|
* struct Foo {
|
|
* ILIST_ENTRY(uint16_t) next;
|
|
* ...
|
|
* }
|
|
*
|
|
*/
|
|
#define ILIST_ENTRY(type) \
|
|
struct { \
|
|
type prev; /* Index of previous element. */ \
|
|
type next; /* Index of next element. */ \
|
|
}
|
|
|
|
#define ILIST_INSERT(pool, head, idx, elem, field) \
|
|
do { \
|
|
typeof(elem) peer; \
|
|
MLX5_ASSERT((elem) && (idx)); \
|
|
(elem)->field.next = *(head); \
|
|
(elem)->field.prev = 0; \
|
|
if (*(head)) { \
|
|
(peer) = mlx5_ipool_get(pool, *(head)); \
|
|
if (peer) \
|
|
(peer)->field.prev = (idx); \
|
|
} \
|
|
*(head) = (idx); \
|
|
} while (0)
|
|
|
|
#define ILIST_REMOVE(pool, head, idx, elem, field) \
|
|
do { \
|
|
typeof(elem) peer; \
|
|
MLX5_ASSERT(elem); \
|
|
MLX5_ASSERT(head); \
|
|
if ((elem)->field.prev) { \
|
|
(peer) = mlx5_ipool_get \
|
|
(pool, (elem)->field.prev); \
|
|
if (peer) \
|
|
(peer)->field.next = (elem)->field.next;\
|
|
} \
|
|
if ((elem)->field.next) { \
|
|
(peer) = mlx5_ipool_get \
|
|
(pool, (elem)->field.next); \
|
|
if (peer) \
|
|
(peer)->field.prev = (elem)->field.prev;\
|
|
} \
|
|
if (*(head) == (idx)) \
|
|
*(head) = (elem)->field.next; \
|
|
} while (0)
|
|
|
|
#define ILIST_FOREACH(pool, head, idx, elem, field) \
|
|
for ((idx) = (head), (elem) = \
|
|
(idx) ? mlx5_ipool_get(pool, (idx)) : NULL; (elem); \
|
|
idx = (elem)->field.next, (elem) = \
|
|
(idx) ? mlx5_ipool_get(pool, idx) : NULL)
|
|
|
|
/* Single index list. */
|
|
#define SILIST_ENTRY(type) \
|
|
struct { \
|
|
type next; /* Index of next element. */ \
|
|
}
|
|
|
|
#define SILIST_INSERT(head, idx, elem, field) \
|
|
do { \
|
|
MLX5_ASSERT((elem) && (idx)); \
|
|
(elem)->field.next = *(head); \
|
|
*(head) = (idx); \
|
|
} while (0)
|
|
|
|
#define SILIST_FOREACH(pool, head, idx, elem, field) \
|
|
for ((idx) = (head), (elem) = \
|
|
(idx) ? mlx5_ipool_get(pool, (idx)) : NULL; (elem); \
|
|
idx = (elem)->field.next, (elem) = \
|
|
(idx) ? mlx5_ipool_get(pool, idx) : NULL)
|
|
|
|
#define MLX5_L3T_FOREACH(tbl, idx, entry) \
|
|
for (idx = 0, (entry) = mlx5_l3t_get_next((tbl), &idx); \
|
|
(entry); \
|
|
idx++, (entry) = mlx5_l3t_get_next((tbl), &idx))
|
|
|
|
#define MLX5_IPOOL_FOREACH(ipool, idx, entry) \
|
|
for ((idx) = 0, mlx5_ipool_flush_cache((ipool)), \
|
|
(entry) = mlx5_ipool_get_next((ipool), &idx); \
|
|
(entry); idx++, (entry) = mlx5_ipool_get_next((ipool), &idx))
|
|
|
|
#endif /* RTE_PMD_MLX5_UTILS_H_ */
|