423c8a2905
This patch renames octeon end point driver from octeontx_ep to octeon_ep to enable single unified driver to support current OcteonTx and future Octeon PCI endpoint NICs to reflect common driver for all Octeon based PCI endpoint NICs. Signed-off-by: Sathesh Edara <sedara@marvell.com> Acked-by: Veerasenareddy Burru <vburru@marvell.com>
142 lines
4.8 KiB
C
142 lines
4.8 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(C) 2021 Marvell.
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*/
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#ifndef _OTX2_EP_VF_H_
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#define _OTX2_EP_VF_H_
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#include <rte_io.h>
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#define SDP_VF_R_IN_CTL_IDLE (0x1ull << 28)
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#define SDP_VF_R_IN_CTL_RDSIZE (0x3ull << 25) /* Setting to max(4) */
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#define SDP_VF_R_IN_CTL_IS_64B (0x1ull << 24)
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#define SDP_VF_R_IN_CTL_ESR (0x1ull << 1)
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#define SDP_VF_BUSY_LOOP_COUNT (10000)
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/* SDP VF OQ Masks */
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#define SDP_VF_R_OUT_CTL_IDLE (1ull << 40)
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#define SDP_VF_R_OUT_CTL_ES_I (1ull << 34)
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#define SDP_VF_R_OUT_CTL_NSR_I (1ull << 33)
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#define SDP_VF_R_OUT_CTL_ROR_I (1ull << 32)
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#define SDP_VF_R_OUT_CTL_ES_D (1ull << 30)
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#define SDP_VF_R_OUT_CTL_NSR_D (1ull << 29)
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#define SDP_VF_R_OUT_CTL_ROR_D (1ull << 28)
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#define SDP_VF_R_OUT_CTL_ES_P (1ull << 26)
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#define SDP_VF_R_OUT_CTL_NSR_P (1ull << 25)
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#define SDP_VF_R_OUT_CTL_ROR_P (1ull << 24)
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#define SDP_VF_R_OUT_CTL_IMODE (1ull << 23)
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/* SDP VF Register definitions */
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#define SDP_VF_RING_OFFSET (0x1ull << 17)
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/* SDP VF IQ Registers */
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#define SDP_VF_R_IN_CONTROL_START (0x10000)
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#define SDP_VF_R_IN_ENABLE_START (0x10010)
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#define SDP_VF_R_IN_INSTR_BADDR_START (0x10020)
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#define SDP_VF_R_IN_INSTR_RSIZE_START (0x10030)
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#define SDP_VF_R_IN_INSTR_DBELL_START (0x10040)
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#define SDP_VF_R_IN_CNTS_START (0x10050)
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#define SDP_VF_R_IN_INT_LEVELS_START (0x10060)
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#define SDP_VF_R_IN_PKT_CNT_START (0x10080)
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#define SDP_VF_R_IN_BYTE_CNT_START (0x10090)
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#define SDP_VF_R_IN_CONTROL(ring) \
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(SDP_VF_R_IN_CONTROL_START + ((ring) * SDP_VF_RING_OFFSET))
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#define SDP_VF_R_IN_ENABLE(ring) \
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(SDP_VF_R_IN_ENABLE_START + ((ring) * SDP_VF_RING_OFFSET))
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#define SDP_VF_R_IN_INSTR_BADDR(ring) \
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(SDP_VF_R_IN_INSTR_BADDR_START + ((ring) * SDP_VF_RING_OFFSET))
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#define SDP_VF_R_IN_INSTR_RSIZE(ring) \
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(SDP_VF_R_IN_INSTR_RSIZE_START + ((ring) * SDP_VF_RING_OFFSET))
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#define SDP_VF_R_IN_INSTR_DBELL(ring) \
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(SDP_VF_R_IN_INSTR_DBELL_START + ((ring) * SDP_VF_RING_OFFSET))
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#define SDP_VF_R_IN_CNTS(ring) \
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(SDP_VF_R_IN_CNTS_START + ((ring) * SDP_VF_RING_OFFSET))
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#define SDP_VF_R_IN_INT_LEVELS(ring) \
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(SDP_VF_R_IN_INT_LEVELS_START + ((ring) * SDP_VF_RING_OFFSET))
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#define SDP_VF_R_IN_PKT_CNT(ring) \
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(SDP_VF_R_IN_PKT_CNT_START + ((ring) * SDP_VF_RING_OFFSET))
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#define SDP_VF_R_IN_BYTE_CNT(ring) \
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(SDP_VF_R_IN_BYTE_CNT_START + ((ring) * SDP_VF_RING_OFFSET))
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/* SDP VF OQ Registers */
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#define SDP_VF_R_OUT_CNTS_START (0x10100)
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#define SDP_VF_R_OUT_INT_LEVELS_START (0x10110)
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#define SDP_VF_R_OUT_SLIST_BADDR_START (0x10120)
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#define SDP_VF_R_OUT_SLIST_RSIZE_START (0x10130)
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#define SDP_VF_R_OUT_SLIST_DBELL_START (0x10140)
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#define SDP_VF_R_OUT_CONTROL_START (0x10150)
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#define SDP_VF_R_OUT_ENABLE_START (0x10160)
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#define SDP_VF_R_OUT_PKT_CNT_START (0x10180)
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#define SDP_VF_R_OUT_BYTE_CNT_START (0x10190)
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#define SDP_VF_R_OUT_CONTROL(ring) \
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(SDP_VF_R_OUT_CONTROL_START + ((ring) * SDP_VF_RING_OFFSET))
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#define SDP_VF_R_OUT_ENABLE(ring) \
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(SDP_VF_R_OUT_ENABLE_START + ((ring) * SDP_VF_RING_OFFSET))
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#define SDP_VF_R_OUT_SLIST_BADDR(ring) \
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(SDP_VF_R_OUT_SLIST_BADDR_START + ((ring) * SDP_VF_RING_OFFSET))
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#define SDP_VF_R_OUT_SLIST_RSIZE(ring) \
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(SDP_VF_R_OUT_SLIST_RSIZE_START + ((ring) * SDP_VF_RING_OFFSET))
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#define SDP_VF_R_OUT_SLIST_DBELL(ring) \
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(SDP_VF_R_OUT_SLIST_DBELL_START + ((ring) * SDP_VF_RING_OFFSET))
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#define SDP_VF_R_OUT_CNTS(ring) \
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(SDP_VF_R_OUT_CNTS_START + ((ring) * SDP_VF_RING_OFFSET))
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#define SDP_VF_R_OUT_INT_LEVELS(ring) \
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(SDP_VF_R_OUT_INT_LEVELS_START + ((ring) * SDP_VF_RING_OFFSET))
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#define SDP_VF_R_OUT_PKT_CNT(ring) \
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(SDP_VF_R_OUT_PKT_CNT_START + ((ring) * SDP_VF_RING_OFFSET))
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#define SDP_VF_R_OUT_BYTE_CNT(ring) \
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(SDP_VF_R_OUT_BYTE_CNT_START + ((ring) * SDP_VF_RING_OFFSET))
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/* SDP VF IQ Masks */
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#define SDP_VF_R_IN_CTL_RPVF_MASK (0xF)
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#define SDP_VF_R_IN_CTL_RPVF_POS (48)
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/* IO Access */
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#define otx2_read64(addr) rte_read64_relaxed((void *)(addr))
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#define otx2_write64(val, addr) rte_write64_relaxed((val), (void *)(addr))
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#define PCI_DEVID_CN9K_EP_NET_VF 0xB203 /* OCTEON 9 EP mode */
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#define PCI_DEVID_CN98XX_EP_NET_VF 0xB103
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int
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otx2_ep_vf_setup_device(struct otx_ep_device *sdpvf);
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struct otx2_ep_instr_64B {
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/* Pointer where the input data is available. */
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uint64_t dptr;
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/* OTX_EP Instruction Header. */
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union otx_ep_instr_ih ih;
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/** Pointer where the response for a RAW mode packet
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* will be written by OCTEON TX.
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*/
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uint64_t rptr;
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/* Input Request Header. */
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union otx_ep_instr_irh irh;
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/* Additional headers available in a 64-byte instruction. */
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uint64_t exhdr[4];
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};
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#endif /*_OTX2_EP_VF_H_ */
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