5e39350912
Adding support for port reconfiguration as user may require to do so on a running system. Signed-off-by: Harman Kalra <hkalra@marvell.com>
189 lines
5.0 KiB
C
189 lines
5.0 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2017 Cavium, Inc
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*/
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#ifndef __OCTEONTX_ETHDEV_H__
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#define __OCTEONTX_ETHDEV_H__
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#include <stdbool.h>
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#include <rte_common.h>
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#include <ethdev_driver.h>
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#include <rte_eventdev.h>
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#include <rte_mempool.h>
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#include <rte_memory.h>
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#include <octeontx_fpavf.h>
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#include "base/octeontx_bgx.h"
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#include "base/octeontx_pki_var.h"
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#include "base/octeontx_pkivf.h"
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#include "base/octeontx_pkovf.h"
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#include "base/octeontx_io.h"
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#define OCTEONTX_PMD net_octeontx
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#define OCTEONTX_VDEV_DEFAULT_MAX_NR_PORT 12
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#define OCTEONTX_VDEV_NR_PORT_ARG ("nr_port")
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#define OCTEONTX_MAX_NAME_LEN 32
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#define OCTEONTX_MAX_BGX_PORTS 4
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#define OCTEONTX_MAX_LMAC_PER_BGX 4
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#define OCCTX_RX_NB_SEG_MAX 6
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#define OCCTX_INTR_POLL_INTERVAL_MS 1000
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/* VLAN tag inserted by OCCTX_TX_VTAG_ACTION.
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* In Tx space is always reserved for this in FRS.
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*/
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#define OCCTX_MAX_VTAG_INS 2
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#define OCCTX_MAX_VTAG_ACT_SIZE (4 * OCCTX_MAX_VTAG_INS)
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/* HW config of frame size doesn't include FCS */
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#define OCCTX_MAX_HW_FRS 9212
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#define OCCTX_MIN_HW_FRS 60
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/* ETH_HLEN+ETH_FCS+2*VLAN_HLEN */
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#define OCCTX_L2_OVERHEAD (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + \
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OCCTX_MAX_VTAG_ACT_SIZE)
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#define OCCTX_L2_MAX_LEN (RTE_ETHER_MTU + OCCTX_L2_OVERHEAD)
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/* Since HW FRS includes NPC VTAG insertion space, user has reduced FRS */
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#define OCCTX_MAX_FRS \
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(OCCTX_MAX_HW_FRS + RTE_ETHER_CRC_LEN - OCCTX_MAX_VTAG_ACT_SIZE)
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#define OCCTX_MIN_FRS (OCCTX_MIN_HW_FRS + RTE_ETHER_CRC_LEN)
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#define OCCTX_MAX_MTU (OCCTX_MAX_FRS - OCCTX_L2_OVERHEAD)
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#define OCTEONTX_RX_OFFLOADS ( \
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RTE_ETH_RX_OFFLOAD_CHECKSUM | \
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RTE_ETH_RX_OFFLOAD_SCTP_CKSUM | \
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RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
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RTE_ETH_RX_OFFLOAD_SCATTER | \
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RTE_ETH_RX_OFFLOAD_SCATTER | \
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RTE_ETH_RX_OFFLOAD_VLAN_FILTER)
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#define OCTEONTX_TX_OFFLOADS ( \
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RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE | \
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RTE_ETH_TX_OFFLOAD_MT_LOCKFREE | \
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RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
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RTE_ETH_TX_OFFLOAD_OUTER_UDP_CKSUM | \
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RTE_ETH_TX_OFFLOAD_IPV4_CKSUM | \
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RTE_ETH_TX_OFFLOAD_TCP_CKSUM | \
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RTE_ETH_TX_OFFLOAD_UDP_CKSUM | \
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RTE_ETH_TX_OFFLOAD_SCTP_CKSUM | \
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RTE_ETH_TX_OFFLOAD_MULTI_SEGS)
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static inline struct octeontx_nic *
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octeontx_pmd_priv(struct rte_eth_dev *dev)
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{
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return dev->data->dev_private;
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}
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extern uint16_t
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rte_octeontx_pchan_map[OCTEONTX_MAX_BGX_PORTS][OCTEONTX_MAX_LMAC_PER_BGX];
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struct vlan_entry {
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TAILQ_ENTRY(vlan_entry) next;
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uint16_t vlan_id;
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};
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TAILQ_HEAD(octeontx_vlan_filter_tbl, vlan_entry);
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struct octeontx_vlan_info {
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struct octeontx_vlan_filter_tbl fltr_tbl;
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uint8_t filter_on;
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};
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struct octeontx_fc_info {
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enum rte_eth_fc_mode mode; /**< Link flow control mode */
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enum rte_eth_fc_mode def_mode;
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uint16_t high_water;
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uint16_t low_water;
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uint16_t def_highmark;
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uint16_t def_lowmark;
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uint32_t rx_fifosz;
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};
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/* Octeontx ethdev nic */
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struct octeontx_nic {
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struct rte_eth_dev *dev;
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int node;
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int port_id;
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int port_ena;
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int base_ichan;
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int num_ichans;
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int base_ochan;
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int num_ochans;
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uint8_t evdev;
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uint8_t bpen;
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uint8_t fcs_strip;
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uint8_t bcast_mode;
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uint8_t mcast_mode;
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uint16_t num_tx_queues;
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uint64_t hwcap;
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uint8_t pko_vfid;
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uint8_t link_up;
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uint8_t duplex;
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uint8_t speed;
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uint16_t bgx_mtu;
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uint16_t mtu;
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uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
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/* Rx port parameters */
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struct {
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bool classifier_enable;
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bool hash_enable;
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bool initialized;
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} pki;
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uint16_t ev_queues;
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uint16_t ev_ports;
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uint64_t rx_offloads;
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uint16_t rx_offload_flags;
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uint64_t tx_offloads;
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uint16_t tx_offload_flags;
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struct octeontx_vlan_info vlan_info;
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int print_flag;
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struct octeontx_fc_info fc;
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bool reconfigure;
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} __rte_cache_aligned;
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struct octeontx_txq {
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uint16_t queue_id;
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octeontx_dq_t dq;
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struct rte_eth_dev *eth_dev;
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} __rte_cache_aligned;
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struct octeontx_rxq {
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uint16_t queue_id;
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uint16_t port_id;
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uint8_t evdev;
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struct rte_eth_dev *eth_dev;
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uint16_t ev_queues;
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uint16_t ev_ports;
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struct rte_mempool *pool;
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} __rte_cache_aligned;
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void
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octeontx_set_tx_function(struct rte_eth_dev *dev);
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/* VLAN */
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int octeontx_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t qidx);
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int octeontx_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t qidx);
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int octeontx_dev_vlan_offload_init(struct rte_eth_dev *dev);
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int octeontx_dev_vlan_offload_fini(struct rte_eth_dev *eth_dev);
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int octeontx_dev_vlan_offload_set(struct rte_eth_dev *dev, int mask);
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int octeontx_dev_vlan_filter_set(struct rte_eth_dev *dev,
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uint16_t vlan_id, int on);
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int octeontx_dev_set_link_up(struct rte_eth_dev *eth_dev);
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int octeontx_dev_set_link_down(struct rte_eth_dev *eth_dev);
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/* Flow control */
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int octeontx_dev_flow_ctrl_init(struct rte_eth_dev *dev);
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int octeontx_dev_flow_ctrl_fini(struct rte_eth_dev *dev);
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int octeontx_dev_flow_ctrl_get(struct rte_eth_dev *dev,
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struct rte_eth_fc_conf *fc_conf);
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int octeontx_dev_flow_ctrl_set(struct rte_eth_dev *dev,
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struct rte_eth_fc_conf *fc_conf);
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#endif /* __OCTEONTX_ETHDEV_H__ */
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