cb0ddabf2f
Split packet processing from packet send stage, as send stage is not common for poll and event mode. Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com> Acked-by: Shijith Thotton <sthotton@marvell.com>
140 lines
3.9 KiB
C
140 lines
3.9 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2010-2016 Intel Corporation
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*/
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#ifndef __L3FWD_LPM_SSE_H__
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#define __L3FWD_LPM_SSE_H__
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#include "l3fwd_sse.h"
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/*
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* Read packet_type and destination IPV4 addresses from 4 mbufs.
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*/
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static inline void
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processx4_step1(struct rte_mbuf *pkt[FWDSTEP],
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__m128i *dip,
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uint32_t *ipv4_flag)
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{
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struct rte_ipv4_hdr *ipv4_hdr;
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struct rte_ether_hdr *eth_hdr;
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uint32_t x0, x1, x2, x3;
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eth_hdr = rte_pktmbuf_mtod(pkt[0], struct rte_ether_hdr *);
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ipv4_hdr = (struct rte_ipv4_hdr *)(eth_hdr + 1);
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x0 = ipv4_hdr->dst_addr;
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ipv4_flag[0] = pkt[0]->packet_type & RTE_PTYPE_L3_IPV4;
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eth_hdr = rte_pktmbuf_mtod(pkt[1], struct rte_ether_hdr *);
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ipv4_hdr = (struct rte_ipv4_hdr *)(eth_hdr + 1);
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x1 = ipv4_hdr->dst_addr;
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ipv4_flag[0] &= pkt[1]->packet_type;
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eth_hdr = rte_pktmbuf_mtod(pkt[2], struct rte_ether_hdr *);
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ipv4_hdr = (struct rte_ipv4_hdr *)(eth_hdr + 1);
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x2 = ipv4_hdr->dst_addr;
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ipv4_flag[0] &= pkt[2]->packet_type;
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eth_hdr = rte_pktmbuf_mtod(pkt[3], struct rte_ether_hdr *);
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ipv4_hdr = (struct rte_ipv4_hdr *)(eth_hdr + 1);
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x3 = ipv4_hdr->dst_addr;
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ipv4_flag[0] &= pkt[3]->packet_type;
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dip[0] = _mm_set_epi32(x3, x2, x1, x0);
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}
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/*
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* Lookup into LPM for destination port.
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* If lookup fails, use incoming port (portid) as destination port.
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*/
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static inline void
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processx4_step2(const struct lcore_conf *qconf,
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__m128i dip,
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uint32_t ipv4_flag,
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uint16_t portid,
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struct rte_mbuf *pkt[FWDSTEP],
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uint16_t dprt[FWDSTEP])
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{
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rte_xmm_t dst;
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const __m128i bswap_mask = _mm_set_epi8(12, 13, 14, 15, 8, 9, 10, 11,
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4, 5, 6, 7, 0, 1, 2, 3);
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/* Byte swap 4 IPV4 addresses. */
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dip = _mm_shuffle_epi8(dip, bswap_mask);
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/* if all 4 packets are IPV4. */
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if (likely(ipv4_flag)) {
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rte_lpm_lookupx4(qconf->ipv4_lookup_struct, dip, dst.u32,
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portid);
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/* get rid of unused upper 16 bit for each dport. */
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dst.x = _mm_packs_epi32(dst.x, dst.x);
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*(uint64_t *)dprt = dst.u64[0];
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} else {
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dst.x = dip;
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dprt[0] = lpm_get_dst_port_with_ipv4(qconf, pkt[0], dst.u32[0], portid);
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dprt[1] = lpm_get_dst_port_with_ipv4(qconf, pkt[1], dst.u32[1], portid);
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dprt[2] = lpm_get_dst_port_with_ipv4(qconf, pkt[2], dst.u32[2], portid);
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dprt[3] = lpm_get_dst_port_with_ipv4(qconf, pkt[3], dst.u32[3], portid);
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}
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}
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/*
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* Buffer optimized handling of packets, invoked
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* from main_loop.
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*/
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static inline void
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l3fwd_lpm_process_packets(int nb_rx, struct rte_mbuf **pkts_burst,
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uint16_t portid, uint16_t *dst_port,
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struct lcore_conf *qconf, const uint8_t do_step3)
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{
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int32_t j;
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__m128i dip[MAX_PKT_BURST / FWDSTEP];
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uint32_t ipv4_flag[MAX_PKT_BURST / FWDSTEP];
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const int32_t k = RTE_ALIGN_FLOOR(nb_rx, FWDSTEP);
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for (j = 0; j != k; j += FWDSTEP)
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processx4_step1(&pkts_burst[j], &dip[j / FWDSTEP],
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&ipv4_flag[j / FWDSTEP]);
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for (j = 0; j != k; j += FWDSTEP)
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processx4_step2(qconf, dip[j / FWDSTEP],
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ipv4_flag[j / FWDSTEP], portid, &pkts_burst[j], &dst_port[j]);
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if (do_step3)
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for (j = 0; j != k; j += FWDSTEP)
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processx4_step3(&pkts_burst[j], &dst_port[j]);
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/* Classify last up to 3 packets one by one */
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switch (nb_rx % FWDSTEP) {
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case 3:
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dst_port[j] = lpm_get_dst_port(qconf, pkts_burst[j], portid);
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if (do_step3)
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process_packet(pkts_burst[j], &dst_port[j]);
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j++;
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/* fall-through */
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case 2:
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dst_port[j] = lpm_get_dst_port(qconf, pkts_burst[j], portid);
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if (do_step3)
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process_packet(pkts_burst[j], &dst_port[j]);
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j++;
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/* fall-through */
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case 1:
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dst_port[j] = lpm_get_dst_port(qconf, pkts_burst[j], portid);
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if (do_step3)
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process_packet(pkts_burst[j], &dst_port[j]);
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j++;
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}
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}
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static inline void
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l3fwd_lpm_send_packets(int nb_rx, struct rte_mbuf **pkts_burst, uint16_t portid,
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struct lcore_conf *qconf)
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{
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uint16_t dst_port[MAX_PKT_BURST];
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l3fwd_lpm_process_packets(nb_rx, pkts_burst, portid, dst_port, qconf,
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0);
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send_packets_multi(qconf, pkts_burst, dst_port, nb_rx);
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}
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#endif /* __L3FWD_LPM_SSE_H__ */
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