3bd122eef2
Adds hardware specific api for all the Chelsio T5 adapters under drivers/net/cxgbe/base directory. Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com> Signed-off-by: Kumar Sanghvi <kumaras@chelsio.com>
346 lines
8.7 KiB
C
346 lines
8.7 KiB
C
/*-
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* BSD LICENSE
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*
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* Copyright(c) 2014-2015 Chelsio Communications.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Chelsio Communications nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef T4_MSG_H
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#define T4_MSG_H
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enum {
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CPL_SGE_EGR_UPDATE = 0xA5,
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CPL_FW4_MSG = 0xC0,
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CPL_FW6_MSG = 0xE0,
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CPL_TX_PKT_LSO = 0xED,
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CPL_TX_PKT_XT = 0xEE,
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};
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enum { /* TX_PKT_XT checksum types */
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TX_CSUM_TCPIP = 8,
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TX_CSUM_UDPIP = 9,
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TX_CSUM_TCPIP6 = 10,
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};
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union opcode_tid {
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__be32 opcode_tid;
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__u8 opcode;
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};
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struct rss_header {
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__u8 opcode;
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#if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
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__u8 channel:2;
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__u8 filter_hit:1;
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__u8 filter_tid:1;
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__u8 hash_type:2;
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__u8 ipv6:1;
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__u8 send2fw:1;
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#else
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__u8 send2fw:1;
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__u8 ipv6:1;
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__u8 hash_type:2;
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__u8 filter_tid:1;
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__u8 filter_hit:1;
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__u8 channel:2;
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#endif
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__be16 qid;
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__be32 hash_val;
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};
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#if defined(RSS_HDR_VLD) || defined(CHELSIO_FW)
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#define RSS_HDR struct rss_header rss_hdr
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#else
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#define RSS_HDR
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#endif
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#ifndef CHELSIO_FW
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struct work_request_hdr {
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__be32 wr_hi;
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__be32 wr_mid;
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__be64 wr_lo;
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};
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#define WR_HDR struct work_request_hdr wr
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#define WR_HDR_SIZE sizeof(struct work_request_hdr)
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#else
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#define WR_HDR
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#define WR_HDR_SIZE 0
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#endif
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struct cpl_tx_data {
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union opcode_tid ot;
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__be32 len;
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__be32 rsvd;
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__be32 flags;
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};
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struct cpl_tx_pkt_core {
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__be32 ctrl0;
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__be16 pack;
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__be16 len;
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__be64 ctrl1;
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};
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struct cpl_tx_pkt {
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WR_HDR;
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struct cpl_tx_pkt_core c;
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};
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/* cpl_tx_pkt_core.ctrl0 fields */
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#define S_TXPKT_PF 8
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#define M_TXPKT_PF 0x7
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#define V_TXPKT_PF(x) ((x) << S_TXPKT_PF)
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#define G_TXPKT_PF(x) (((x) >> S_TXPKT_PF) & M_TXPKT_PF)
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#define S_TXPKT_INTF 16
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#define M_TXPKT_INTF 0xF
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#define V_TXPKT_INTF(x) ((x) << S_TXPKT_INTF)
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#define G_TXPKT_INTF(x) (((x) >> S_TXPKT_INTF) & M_TXPKT_INTF)
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#define S_TXPKT_OPCODE 24
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#define M_TXPKT_OPCODE 0xFF
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#define V_TXPKT_OPCODE(x) ((x) << S_TXPKT_OPCODE)
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#define G_TXPKT_OPCODE(x) (((x) >> S_TXPKT_OPCODE) & M_TXPKT_OPCODE)
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/* cpl_tx_pkt_core.ctrl1 fields */
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#define S_TXPKT_IPHDR_LEN 20
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#define M_TXPKT_IPHDR_LEN 0x3FFF
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#define V_TXPKT_IPHDR_LEN(x) ((__u64)(x) << S_TXPKT_IPHDR_LEN)
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#define G_TXPKT_IPHDR_LEN(x) (((x) >> S_TXPKT_IPHDR_LEN) & M_TXPKT_IPHDR_LEN)
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#define S_TXPKT_ETHHDR_LEN 34
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#define M_TXPKT_ETHHDR_LEN 0x3F
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#define V_TXPKT_ETHHDR_LEN(x) ((__u64)(x) << S_TXPKT_ETHHDR_LEN)
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#define G_TXPKT_ETHHDR_LEN(x) (((x) >> S_TXPKT_ETHHDR_LEN) & M_TXPKT_ETHHDR_LEN)
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#define S_T6_TXPKT_ETHHDR_LEN 32
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#define M_T6_TXPKT_ETHHDR_LEN 0xFF
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#define V_T6_TXPKT_ETHHDR_LEN(x) ((__u64)(x) << S_T6_TXPKT_ETHHDR_LEN)
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#define G_T6_TXPKT_ETHHDR_LEN(x) \
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(((x) >> S_T6_TXPKT_ETHHDR_LEN) & M_T6_TXPKT_ETHHDR_LEN)
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#define S_TXPKT_CSUM_TYPE 40
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#define M_TXPKT_CSUM_TYPE 0xF
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#define V_TXPKT_CSUM_TYPE(x) ((__u64)(x) << S_TXPKT_CSUM_TYPE)
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#define G_TXPKT_CSUM_TYPE(x) (((x) >> S_TXPKT_CSUM_TYPE) & M_TXPKT_CSUM_TYPE)
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#define S_TXPKT_VLAN 44
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#define M_TXPKT_VLAN 0xFFFF
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#define V_TXPKT_VLAN(x) ((__u64)(x) << S_TXPKT_VLAN)
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#define G_TXPKT_VLAN(x) (((x) >> S_TXPKT_VLAN) & M_TXPKT_VLAN)
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#define S_TXPKT_VLAN_VLD 60
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#define V_TXPKT_VLAN_VLD(x) ((__u64)(x) << S_TXPKT_VLAN_VLD)
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#define F_TXPKT_VLAN_VLD V_TXPKT_VLAN_VLD(1ULL)
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#define S_TXPKT_IPCSUM_DIS 62
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#define V_TXPKT_IPCSUM_DIS(x) ((__u64)(x) << S_TXPKT_IPCSUM_DIS)
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#define F_TXPKT_IPCSUM_DIS V_TXPKT_IPCSUM_DIS(1ULL)
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#define S_TXPKT_L4CSUM_DIS 63
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#define V_TXPKT_L4CSUM_DIS(x) ((__u64)(x) << S_TXPKT_L4CSUM_DIS)
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#define F_TXPKT_L4CSUM_DIS V_TXPKT_L4CSUM_DIS(1ULL)
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struct cpl_tx_pkt_lso_core {
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__be32 lso_ctrl;
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__be16 ipid_ofst;
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__be16 mss;
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__be32 seqno_offset;
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__be32 len;
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/* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */
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};
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struct cpl_tx_pkt_lso {
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WR_HDR;
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struct cpl_tx_pkt_lso_core c;
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/* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */
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};
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/* cpl_tx_pkt_lso_core.lso_ctrl fields */
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#define S_LSO_TCPHDR_LEN 0
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#define M_LSO_TCPHDR_LEN 0xF
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#define V_LSO_TCPHDR_LEN(x) ((x) << S_LSO_TCPHDR_LEN)
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#define G_LSO_TCPHDR_LEN(x) (((x) >> S_LSO_TCPHDR_LEN) & M_LSO_TCPHDR_LEN)
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#define S_LSO_IPHDR_LEN 4
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#define M_LSO_IPHDR_LEN 0xFFF
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#define V_LSO_IPHDR_LEN(x) ((x) << S_LSO_IPHDR_LEN)
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#define G_LSO_IPHDR_LEN(x) (((x) >> S_LSO_IPHDR_LEN) & M_LSO_IPHDR_LEN)
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#define S_LSO_ETHHDR_LEN 16
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#define M_LSO_ETHHDR_LEN 0xF
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#define V_LSO_ETHHDR_LEN(x) ((x) << S_LSO_ETHHDR_LEN)
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#define G_LSO_ETHHDR_LEN(x) (((x) >> S_LSO_ETHHDR_LEN) & M_LSO_ETHHDR_LEN)
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#define S_LSO_IPV6 20
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#define V_LSO_IPV6(x) ((x) << S_LSO_IPV6)
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#define F_LSO_IPV6 V_LSO_IPV6(1U)
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#define S_LSO_LAST_SLICE 22
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#define V_LSO_LAST_SLICE(x) ((x) << S_LSO_LAST_SLICE)
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#define F_LSO_LAST_SLICE V_LSO_LAST_SLICE(1U)
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#define S_LSO_FIRST_SLICE 23
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#define V_LSO_FIRST_SLICE(x) ((x) << S_LSO_FIRST_SLICE)
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#define F_LSO_FIRST_SLICE V_LSO_FIRST_SLICE(1U)
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#define S_LSO_OPCODE 24
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#define M_LSO_OPCODE 0xFF
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#define V_LSO_OPCODE(x) ((x) << S_LSO_OPCODE)
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#define G_LSO_OPCODE(x) (((x) >> S_LSO_OPCODE) & M_LSO_OPCODE)
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#define S_LSO_T5_XFER_SIZE 0
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#define M_LSO_T5_XFER_SIZE 0xFFFFFFF
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#define V_LSO_T5_XFER_SIZE(x) ((x) << S_LSO_T5_XFER_SIZE)
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#define G_LSO_T5_XFER_SIZE(x) (((x) >> S_LSO_T5_XFER_SIZE) & M_LSO_T5_XFER_SIZE)
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struct cpl_rx_pkt {
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RSS_HDR;
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__u8 opcode;
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#if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
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__u8 iff:4;
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__u8 csum_calc:1;
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__u8 ipmi_pkt:1;
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__u8 vlan_ex:1;
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__u8 ip_frag:1;
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#else
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__u8 ip_frag:1;
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__u8 vlan_ex:1;
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__u8 ipmi_pkt:1;
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__u8 csum_calc:1;
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__u8 iff:4;
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#endif
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__be16 csum;
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__be16 vlan;
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__be16 len;
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__be32 l2info;
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__be16 hdr_len;
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__be16 err_vec;
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};
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/* rx_pkt.l2info fields */
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#define S_RXF_UDP 22
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#define V_RXF_UDP(x) ((x) << S_RXF_UDP)
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#define F_RXF_UDP V_RXF_UDP(1U)
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#define S_RXF_TCP 23
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#define V_RXF_TCP(x) ((x) << S_RXF_TCP)
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#define F_RXF_TCP V_RXF_TCP(1U)
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#define S_RXF_IP 24
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#define V_RXF_IP(x) ((x) << S_RXF_IP)
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#define F_RXF_IP V_RXF_IP(1U)
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#define S_RXF_IP6 25
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#define V_RXF_IP6(x) ((x) << S_RXF_IP6)
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#define F_RXF_IP6 V_RXF_IP6(1U)
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/* cpl_fw*.type values */
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enum {
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FW_TYPE_RSSCPL = 4,
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};
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struct cpl_fw4_msg {
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RSS_HDR;
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u8 opcode;
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u8 type;
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__be16 rsvd0;
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__be32 rsvd1;
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__be64 data[2];
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};
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struct cpl_fw6_msg {
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RSS_HDR;
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u8 opcode;
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u8 type;
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__be16 rsvd0;
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__be32 rsvd1;
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__be64 data[4];
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};
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enum {
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ULP_TX_SC_IMM = 0x81,
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ULP_TX_SC_DSGL = 0x82,
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ULP_TX_SC_ISGL = 0x83
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};
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#define S_ULPTX_CMD 24
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#define M_ULPTX_CMD 0xFF
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#define V_ULPTX_CMD(x) ((x) << S_ULPTX_CMD)
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#define S_ULP_TX_SC_MORE 23
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#define V_ULP_TX_SC_MORE(x) ((x) << S_ULP_TX_SC_MORE)
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#define F_ULP_TX_SC_MORE V_ULP_TX_SC_MORE(1U)
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struct ulptx_sge_pair {
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__be32 len[2];
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__be64 addr[2];
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};
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struct ulptx_sgl {
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__be32 cmd_nsge;
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__be32 len0;
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__be64 addr0;
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#if !(defined C99_NOT_SUPPORTED)
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struct ulptx_sge_pair sge[0];
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#endif
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};
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struct ulptx_idata {
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__be32 cmd_more;
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__be32 len;
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};
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#define S_ULPTX_NSGE 0
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#define M_ULPTX_NSGE 0xFFFF
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#define V_ULPTX_NSGE(x) ((x) << S_ULPTX_NSGE)
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struct ulp_txpkt {
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__be32 cmd_dest;
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__be32 len;
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};
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/* ulp_txpkt.cmd_dest fields */
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#define S_ULP_TXPKT_DEST 16
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#define M_ULP_TXPKT_DEST 0x3
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#define V_ULP_TXPKT_DEST(x) ((x) << S_ULP_TXPKT_DEST)
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#define S_ULP_TXPKT_FID 4
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#define M_ULP_TXPKT_FID 0x7ff
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#define V_ULP_TXPKT_FID(x) ((x) << S_ULP_TXPKT_FID)
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#define S_ULP_TXPKT_RO 3
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#define V_ULP_TXPKT_RO(x) ((x) << S_ULP_TXPKT_RO)
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#define F_ULP_TXPKT_RO V_ULP_TXPKT_RO(1U)
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#endif /* T4_MSG_H */
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