f8aadb64df
All rights reserved by Beijing Wangxun Technology Co., Ltd. Part of the code references Intel. Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com> Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
67 lines
2.6 KiB
C
67 lines
2.6 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2015-2020 Beijing WangXun Technology Co., Ltd.
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* Copyright(c) 2010-2017 Intel Corporation
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*/
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#ifndef _TXGBE_EEPROM_H_
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#define _TXGBE_EEPROM_H_
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/* Checksum and EEPROM pointers */
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#define TXGBE_PBANUM_PTR_GUARD 0xFAFA
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#define TXGBE_EEPROM_SUM 0xBABA
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#define TXGBE_FW_VER_LEN 32
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#define TXGBE_FW_N_TXEQ 0x0002000A
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#define TXGBE_FW_PTR 0x0F
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#define TXGBE_PBANUM0_PTR 0x05
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#define TXGBE_PBANUM1_PTR 0x06
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#define TXGBE_SW_REGION_PTR 0x1C
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#define TXGBE_EE_CSUM_MAX 0x800
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#define TXGBE_EEPROM_CHECKSUM 0x2F
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#define TXGBE_SAN_MAC_ADDR_PTR 0x18
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#define TXGBE_DEVICE_CAPS 0x1C
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#define TXGBE_EEPROM_VERSION_L 0x1D
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#define TXGBE_EEPROM_VERSION_H 0x1E
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#define TXGBE_ISCSI_BOOT_CONFIG 0x07
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#define TXGBE_SAN_MAC_ADDR_PORT0_OFFSET 0x0
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#define TXGBE_SAN_MAC_ADDR_PORT1_OFFSET 0x3
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#define TXGBE_DEVICE_CAPS_ALLOW_ANY_SFP 0x1
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#define TXGBE_DEVICE_CAPS_NO_CROSSTALK_WR (1 << 7)
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#define TXGBE_FW_LESM_PARAMETERS_PTR 0x2
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#define TXGBE_FW_LESM_STATE_1 0x1
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#define TXGBE_FW_LESM_STATE_ENABLED 0x8000 /* LESM Enable bit */
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#define TXGBE_ALT_SAN_MAC_ADDR_BLK_PTR 0x27 /* Alt. SAN MAC block */
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#define TXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET 0x0 /* Alt SAN MAC capability */
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#define TXGBE_ALT_SAN_MAC_ADDR_PORT0_OFFSET 0x1 /* Alt SAN MAC 0 offset */
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#define TXGBE_ALT_SAN_MAC_ADDR_PORT1_OFFSET 0x4 /* Alt SAN MAC 1 offset */
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#define TXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET 0x7 /* Alt WWNN prefix offset */
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#define TXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET 0x8 /* Alt WWPN prefix offset */
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#define TXGBE_ALT_SAN_MAC_ADDR_CAPS_SANMAC 0x0 /* Alt SAN MAC exists */
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#define TXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN 0x1 /* Alt WWN base exists */
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s32 txgbe_init_eeprom_params(struct txgbe_hw *hw);
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s32 txgbe_calc_eeprom_checksum(struct txgbe_hw *hw);
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s32 txgbe_validate_eeprom_checksum(struct txgbe_hw *hw, u16 *checksum_val);
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s32 txgbe_update_eeprom_checksum(struct txgbe_hw *hw);
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s32 txgbe_get_eeprom_semaphore(struct txgbe_hw *hw);
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void txgbe_release_eeprom_semaphore(struct txgbe_hw *hw);
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s32 txgbe_ee_read16(struct txgbe_hw *hw, u32 offset, u16 *data);
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s32 txgbe_ee_readw_sw(struct txgbe_hw *hw, u32 offset, u16 *data);
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s32 txgbe_ee_readw_buffer(struct txgbe_hw *hw, u32 offset, u32 words,
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void *data);
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s32 txgbe_ee_read32(struct txgbe_hw *hw, u32 addr, u32 *data);
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s32 txgbe_ee_write16(struct txgbe_hw *hw, u32 offset, u16 data);
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s32 txgbe_ee_writew_sw(struct txgbe_hw *hw, u32 offset, u16 data);
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s32 txgbe_ee_writew_buffer(struct txgbe_hw *hw, u32 offset, u32 words,
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void *data);
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s32 txgbe_ee_write32(struct txgbe_hw *hw, u32 addr, u32 data);
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#endif /* _TXGBE_EEPROM_H_ */
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