9f34c5a7ab
On TILE-Gx and TILE-Mx platforms, the buffers fed into the hardware buffer manager require a 128-byte alignment. With this change, we allow configuration based override of the element alignment, and default to RTE_CACHE_LINE_SIZE if left unspecified. Signed-off-by: Cyril Chemparathy <cchemparathy@ezchip.com> Signed-off-by: Zhigang Lu <zlu@ezchip.com> Acked-by: Bruce Richardson <bruce.richardson@intel.com> |
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Makefile | ||
rte_dom0_mempool.c | ||
rte_mempool_version.map | ||
rte_mempool.c | ||
rte_mempool.h |