f22e705ebf
Add all necessary elements for DPDK to compile and run EAL on SiFive Freedom U740 SoC which is based on SiFive U74-MC (ISA: rv64imafdc) core complex. This includes: - EAL library implementation for rv64imafdc ISA. - meson build structure for 'riscv' architecture. RTE_ARCH_RISCV define is added for architecture identification. - xmm_t structure operation stubs as there is no vector support in the U74 core. Compilation was tested on Ubuntu and Arch Linux using riscv64 toolchain. Clang compilation currently not supported due to issues with missing relocation relaxation. Two rte_rdtsc() schemes are provided: stable low-resolution using rdtime (default) and unstable high-resolution using rdcycle. User can override the scheme by defining RTE_RISCV_RDTSC_USE_HPM=1 during compile time of both DPDK and the application. The reasoning for this is as follows. The RISC-V ISA mandates that clock read by rdtime has to be of constant period and synchronized between all hardware threads within 1 tick (chapter 10.1 in version 20191213 of RISC-V spec). However this clock may not be of high-enough frequency for dataplane uses. I.e. on HiFive Unmatched (FU740) it is 1MHz. There is a high-resolution alternative in form of rdcycle which is clocked at the core clock frequency. The drawbacks are that it may be disabled during sleep (WFI), its frequency might change due to DVFS and it is core-local and therefore cannot be used as a wall-clock. It can however be used for micro-benchmarking user applications, similarly to Aarch64's PMCCNTR PMU counter. The platform is currently marked as linux-only because rte_cycles implementation uses the timebase-frequency device-tree node read through the proc file system. Such approach was chosen because Linux kernel depends on the presence of this device-tree node. The i40e PMD driver is disabled on RISC-V as the rv64gc ISA has no vector operations. The compilation of following modules has been disabled by this commit and will be re-enabled in later commits as fixes are introduced: net/ixgbe, net/memif, net/tap, example/l3fwd. Sponsored-by: Frank Zhao <frank.zhao@starfivetech.com> Sponsored-by: Sam Grove <sam.grove@sifive.com> Signed-off-by: Michal Mazurek <maz@semihalf.com> Signed-off-by: Stanislaw Kardach <kda@semihalf.com>
123 lines
2.8 KiB
C
123 lines
2.8 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2022 StarFive
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* Copyright(c) 2022 SiFive
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* Copyright(c) 2022 Semihalf
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*/
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#include "rte_cpuflags.h"
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#include <elf.h>
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#include <fcntl.h>
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#include <assert.h>
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#include <unistd.h>
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#include <string.h>
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#ifndef AT_HWCAP
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#define AT_HWCAP 16
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#endif
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#ifndef AT_HWCAP2
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#define AT_HWCAP2 26
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#endif
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#ifndef AT_PLATFORM
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#define AT_PLATFORM 15
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#endif
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enum cpu_register_t {
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REG_NONE = 0,
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REG_HWCAP,
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REG_HWCAP2,
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REG_PLATFORM,
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REG_MAX
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};
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typedef uint32_t hwcap_registers_t[REG_MAX];
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/**
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* Struct to hold a processor feature entry
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*/
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struct feature_entry {
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uint32_t reg;
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uint32_t bit;
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#define CPU_FLAG_NAME_MAX_LEN 64
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char name[CPU_FLAG_NAME_MAX_LEN];
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};
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#define FEAT_DEF(name, reg, bit) \
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[RTE_CPUFLAG_##name] = {reg, bit, #name},
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typedef Elf64_auxv_t _Elfx_auxv_t;
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const struct feature_entry rte_cpu_feature_table[] = {
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FEAT_DEF(RISCV_ISA_A, REG_HWCAP, 0)
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FEAT_DEF(RISCV_ISA_B, REG_HWCAP, 1)
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FEAT_DEF(RISCV_ISA_C, REG_HWCAP, 2)
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FEAT_DEF(RISCV_ISA_D, REG_HWCAP, 3)
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FEAT_DEF(RISCV_ISA_E, REG_HWCAP, 4)
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FEAT_DEF(RISCV_ISA_F, REG_HWCAP, 5)
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FEAT_DEF(RISCV_ISA_G, REG_HWCAP, 6)
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FEAT_DEF(RISCV_ISA_H, REG_HWCAP, 7)
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FEAT_DEF(RISCV_ISA_I, REG_HWCAP, 8)
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FEAT_DEF(RISCV_ISA_J, REG_HWCAP, 9)
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FEAT_DEF(RISCV_ISA_K, REG_HWCAP, 10)
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FEAT_DEF(RISCV_ISA_L, REG_HWCAP, 11)
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FEAT_DEF(RISCV_ISA_M, REG_HWCAP, 12)
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FEAT_DEF(RISCV_ISA_N, REG_HWCAP, 13)
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FEAT_DEF(RISCV_ISA_O, REG_HWCAP, 14)
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FEAT_DEF(RISCV_ISA_P, REG_HWCAP, 15)
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FEAT_DEF(RISCV_ISA_Q, REG_HWCAP, 16)
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FEAT_DEF(RISCV_ISA_R, REG_HWCAP, 17)
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FEAT_DEF(RISCV_ISA_S, REG_HWCAP, 18)
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FEAT_DEF(RISCV_ISA_T, REG_HWCAP, 19)
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FEAT_DEF(RISCV_ISA_U, REG_HWCAP, 20)
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FEAT_DEF(RISCV_ISA_V, REG_HWCAP, 21)
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FEAT_DEF(RISCV_ISA_W, REG_HWCAP, 22)
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FEAT_DEF(RISCV_ISA_X, REG_HWCAP, 23)
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FEAT_DEF(RISCV_ISA_Y, REG_HWCAP, 24)
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FEAT_DEF(RISCV_ISA_Z, REG_HWCAP, 25)
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};
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/*
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* Read AUXV software register and get cpu features for ARM
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*/
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static void
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rte_cpu_get_features(hwcap_registers_t out)
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{
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out[REG_HWCAP] = rte_cpu_getauxval(AT_HWCAP);
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out[REG_HWCAP2] = rte_cpu_getauxval(AT_HWCAP2);
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}
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/*
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* Checks if a particular flag is available on current machine.
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*/
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int
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rte_cpu_get_flag_enabled(enum rte_cpu_flag_t feature)
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{
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const struct feature_entry *feat;
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hwcap_registers_t regs = {0};
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if (feature >= RTE_CPUFLAG_NUMFLAGS)
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return -ENOENT;
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feat = &rte_cpu_feature_table[feature];
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if (feat->reg == REG_NONE)
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return -EFAULT;
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rte_cpu_get_features(regs);
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return (regs[feat->reg] >> feat->bit) & 1;
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}
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const char *
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rte_cpu_get_flag_name(enum rte_cpu_flag_t feature)
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{
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if (feature >= RTE_CPUFLAG_NUMFLAGS)
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return NULL;
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return rte_cpu_feature_table[feature].name;
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}
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void
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rte_cpu_get_intrinsics_support(struct rte_cpu_intrinsics *intrinsics)
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{
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memset(intrinsics, 0, sizeof(*intrinsics));
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}
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