32e4930d5a
Add hardware queue management code corresponding to queue pair setup and release functions. Signed-off-by: Nagadheeraj Rottela <rnagadheeraj@marvell.com> Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
116 lines
2.6 KiB
C
116 lines
2.6 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(C) 2019 Marvell International Ltd.
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*/
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#include <rte_cryptodev.h>
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#include <rte_malloc.h>
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#include "nitrox_qp.h"
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#include "nitrox_hal.h"
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#include "nitrox_logs.h"
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#define MAX_CMD_QLEN 16384
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#define CMDQ_PKT_IN_ALIGN 16
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static int
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nitrox_setup_cmdq(struct nitrox_qp *qp, uint8_t *bar_addr,
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const char *dev_name, uint8_t instr_size, int socket_id)
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{
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char mz_name[RTE_MEMZONE_NAMESIZE];
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const struct rte_memzone *mz;
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size_t cmdq_size = qp->count * instr_size;
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uint64_t offset;
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snprintf(mz_name, sizeof(mz_name), "%s_cmdq_%d", dev_name, qp->qno);
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mz = rte_memzone_reserve_aligned(mz_name, cmdq_size, socket_id,
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RTE_MEMZONE_SIZE_HINT_ONLY |
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RTE_MEMZONE_256MB,
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CMDQ_PKT_IN_ALIGN);
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if (!mz) {
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NITROX_LOG(ERR, "cmdq memzone reserve failed for %s queue\n",
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mz_name);
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return -ENOMEM;
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}
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qp->cmdq.mz = mz;
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offset = NPS_PKT_IN_INSTR_BAOFF_DBELLX(qp->qno);
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qp->cmdq.dbell_csr_addr = NITROX_CSR_ADDR(bar_addr, offset);
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qp->cmdq.ring = mz->addr;
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qp->cmdq.instr_size = instr_size;
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setup_nps_pkt_input_ring(bar_addr, qp->qno, qp->count, mz->iova);
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setup_nps_pkt_solicit_output_port(bar_addr, qp->qno);
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return 0;
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}
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static int
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nitrox_setup_ridq(struct nitrox_qp *qp, int socket_id)
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{
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size_t ridq_size = qp->count * sizeof(*qp->ridq);
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qp->ridq = rte_zmalloc_socket("nitrox ridq", ridq_size,
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RTE_CACHE_LINE_SIZE,
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socket_id);
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if (!qp->ridq) {
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NITROX_LOG(ERR, "Failed to create rid queue\n");
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return -ENOMEM;
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}
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return 0;
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}
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static int
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nitrox_release_cmdq(struct nitrox_qp *qp, uint8_t *bar_addr)
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{
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nps_pkt_solicited_port_disable(bar_addr, qp->qno);
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nps_pkt_input_ring_disable(bar_addr, qp->qno);
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return rte_memzone_free(qp->cmdq.mz);
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}
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int
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nitrox_qp_setup(struct nitrox_qp *qp, uint8_t *bar_addr, const char *dev_name,
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uint32_t nb_descriptors, uint8_t instr_size, int socket_id)
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{
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int err;
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uint32_t count;
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count = rte_align32pow2(nb_descriptors);
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if (count > MAX_CMD_QLEN) {
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NITROX_LOG(ERR, "%s: Number of descriptors too big %d,"
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" greater than max queue length %d\n",
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dev_name, count,
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MAX_CMD_QLEN);
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return -EINVAL;
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}
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qp->count = count;
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qp->head = qp->tail = 0;
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rte_atomic16_init(&qp->pending_count);
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err = nitrox_setup_cmdq(qp, bar_addr, dev_name, instr_size, socket_id);
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if (err)
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return err;
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err = nitrox_setup_ridq(qp, socket_id);
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if (err)
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goto ridq_err;
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return 0;
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ridq_err:
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nitrox_release_cmdq(qp, bar_addr);
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return err;
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}
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static void
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nitrox_release_ridq(struct nitrox_qp *qp)
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{
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rte_free(qp->ridq);
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}
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int
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nitrox_qp_release(struct nitrox_qp *qp, uint8_t *bar_addr)
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{
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nitrox_release_ridq(qp);
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return nitrox_release_cmdq(qp, bar_addr);
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}
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