678f3eca1d
This patch adds cipher only crypto operation support. Signed-off-by: Nagadheeraj Rottela <rnagadheeraj@marvell.com>
801 lines
19 KiB
C
801 lines
19 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(C) 2019 Marvell International Ltd.
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*/
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#include <stdbool.h>
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#include <rte_cryptodev_pmd.h>
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#include <rte_crypto.h>
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#include "nitrox_sym.h"
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#include "nitrox_device.h"
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#include "nitrox_sym_capabilities.h"
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#include "nitrox_qp.h"
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#include "nitrox_sym_reqmgr.h"
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#include "nitrox_sym_ctx.h"
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#include "nitrox_logs.h"
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#define CRYPTODEV_NAME_NITROX_PMD crypto_nitrox_sym
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#define MC_MAC_MISMATCH_ERR_CODE 0x4c
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#define NPS_PKT_IN_INSTR_SIZE 64
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#define IV_FROM_DPTR 1
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#define FLEXI_CRYPTO_ENCRYPT_HMAC 0x33
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#define FLEXI_CRYPTO_MAX_AAD_LEN 512
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#define AES_KEYSIZE_128 16
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#define AES_KEYSIZE_192 24
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#define AES_KEYSIZE_256 32
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#define MAX_IV_LEN 16
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struct nitrox_sym_device {
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struct rte_cryptodev *cdev;
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struct nitrox_device *ndev;
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};
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/* Cipher opcodes */
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enum flexi_cipher {
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CIPHER_NULL = 0,
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CIPHER_3DES_CBC,
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CIPHER_3DES_ECB,
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CIPHER_AES_CBC,
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CIPHER_AES_ECB,
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CIPHER_AES_CFB,
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CIPHER_AES_CTR,
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CIPHER_AES_GCM,
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CIPHER_AES_XTS,
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CIPHER_AES_CCM,
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CIPHER_AES_CBC_CTS,
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CIPHER_AES_ECB_CTS,
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CIPHER_INVALID
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};
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/* Auth opcodes */
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enum flexi_auth {
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AUTH_NULL = 0,
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AUTH_MD5,
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AUTH_SHA1,
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AUTH_SHA2_SHA224,
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AUTH_SHA2_SHA256,
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AUTH_SHA2_SHA384,
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AUTH_SHA2_SHA512,
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AUTH_GMAC,
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AUTH_INVALID
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};
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uint8_t nitrox_sym_drv_id;
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static const char nitrox_sym_drv_name[] = RTE_STR(CRYPTODEV_NAME_NITROX_PMD);
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static const struct rte_driver nitrox_rte_sym_drv = {
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.name = nitrox_sym_drv_name,
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.alias = nitrox_sym_drv_name
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};
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static int nitrox_sym_dev_qp_release(struct rte_cryptodev *cdev,
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uint16_t qp_id);
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static int
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nitrox_sym_dev_config(struct rte_cryptodev *cdev,
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struct rte_cryptodev_config *config)
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{
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struct nitrox_sym_device *sym_dev = cdev->data->dev_private;
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struct nitrox_device *ndev = sym_dev->ndev;
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if (config->nb_queue_pairs > ndev->nr_queues) {
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NITROX_LOG(ERR, "Invalid queue pairs, max supported %d\n",
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ndev->nr_queues);
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return -EINVAL;
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}
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return 0;
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}
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static int
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nitrox_sym_dev_start(struct rte_cryptodev *cdev)
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{
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/* SE cores initialization is done in PF */
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RTE_SET_USED(cdev);
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return 0;
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}
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static void
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nitrox_sym_dev_stop(struct rte_cryptodev *cdev)
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{
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/* SE cores cleanup is done in PF */
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RTE_SET_USED(cdev);
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}
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static int
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nitrox_sym_dev_close(struct rte_cryptodev *cdev)
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{
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int i, ret;
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for (i = 0; i < cdev->data->nb_queue_pairs; i++) {
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ret = nitrox_sym_dev_qp_release(cdev, i);
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if (ret)
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return ret;
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}
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return 0;
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}
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static void
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nitrox_sym_dev_info_get(struct rte_cryptodev *cdev,
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struct rte_cryptodev_info *info)
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{
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struct nitrox_sym_device *sym_dev = cdev->data->dev_private;
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struct nitrox_device *ndev = sym_dev->ndev;
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if (!info)
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return;
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info->max_nb_queue_pairs = ndev->nr_queues;
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info->feature_flags = cdev->feature_flags;
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info->capabilities = nitrox_get_sym_capabilities();
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info->driver_id = nitrox_sym_drv_id;
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info->sym.max_nb_sessions = 0;
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}
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static void
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nitrox_sym_dev_stats_get(struct rte_cryptodev *cdev,
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struct rte_cryptodev_stats *stats)
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{
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int qp_id;
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for (qp_id = 0; qp_id < cdev->data->nb_queue_pairs; qp_id++) {
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struct nitrox_qp *qp = cdev->data->queue_pairs[qp_id];
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if (!qp)
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continue;
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stats->enqueued_count += qp->stats.enqueued_count;
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stats->dequeued_count += qp->stats.dequeued_count;
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stats->enqueue_err_count += qp->stats.enqueue_err_count;
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stats->dequeue_err_count += qp->stats.dequeue_err_count;
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}
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}
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static void
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nitrox_sym_dev_stats_reset(struct rte_cryptodev *cdev)
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{
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int qp_id;
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for (qp_id = 0; qp_id < cdev->data->nb_queue_pairs; qp_id++) {
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struct nitrox_qp *qp = cdev->data->queue_pairs[qp_id];
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if (!qp)
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continue;
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memset(&qp->stats, 0, sizeof(qp->stats));
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}
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}
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static int
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nitrox_sym_dev_qp_setup(struct rte_cryptodev *cdev, uint16_t qp_id,
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const struct rte_cryptodev_qp_conf *qp_conf,
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int socket_id)
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{
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struct nitrox_sym_device *sym_dev = cdev->data->dev_private;
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struct nitrox_device *ndev = sym_dev->ndev;
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struct nitrox_qp *qp = NULL;
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int err;
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NITROX_LOG(DEBUG, "queue %d\n", qp_id);
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if (qp_id >= ndev->nr_queues) {
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NITROX_LOG(ERR, "queue %u invalid, max queues supported %d\n",
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qp_id, ndev->nr_queues);
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return -EINVAL;
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}
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if (cdev->data->queue_pairs[qp_id]) {
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err = nitrox_sym_dev_qp_release(cdev, qp_id);
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if (err)
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return err;
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}
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qp = rte_zmalloc_socket("nitrox PMD qp", sizeof(*qp),
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RTE_CACHE_LINE_SIZE,
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socket_id);
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if (!qp) {
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NITROX_LOG(ERR, "Failed to allocate nitrox qp\n");
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return -ENOMEM;
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}
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qp->qno = qp_id;
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err = nitrox_qp_setup(qp, ndev->bar_addr, cdev->data->name,
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qp_conf->nb_descriptors, NPS_PKT_IN_INSTR_SIZE,
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socket_id);
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if (unlikely(err))
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goto qp_setup_err;
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qp->sr_mp = nitrox_sym_req_pool_create(cdev, qp->count, qp_id,
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socket_id);
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if (unlikely(!qp->sr_mp))
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goto req_pool_err;
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cdev->data->queue_pairs[qp_id] = qp;
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NITROX_LOG(DEBUG, "queue %d setup done\n", qp_id);
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return 0;
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req_pool_err:
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nitrox_qp_release(qp, ndev->bar_addr);
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qp_setup_err:
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rte_free(qp);
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return err;
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}
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static int
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nitrox_sym_dev_qp_release(struct rte_cryptodev *cdev, uint16_t qp_id)
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{
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struct nitrox_sym_device *sym_dev = cdev->data->dev_private;
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struct nitrox_device *ndev = sym_dev->ndev;
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struct nitrox_qp *qp;
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int err;
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NITROX_LOG(DEBUG, "queue %d\n", qp_id);
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if (qp_id >= ndev->nr_queues) {
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NITROX_LOG(ERR, "queue %u invalid, max queues supported %d\n",
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qp_id, ndev->nr_queues);
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return -EINVAL;
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}
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qp = cdev->data->queue_pairs[qp_id];
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if (!qp) {
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NITROX_LOG(DEBUG, "queue %u already freed\n", qp_id);
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return 0;
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}
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if (!nitrox_qp_is_empty(qp)) {
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NITROX_LOG(ERR, "queue %d not empty\n", qp_id);
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return -EAGAIN;
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}
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cdev->data->queue_pairs[qp_id] = NULL;
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err = nitrox_qp_release(qp, ndev->bar_addr);
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nitrox_sym_req_pool_free(qp->sr_mp);
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rte_free(qp);
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NITROX_LOG(DEBUG, "queue %d release done\n", qp_id);
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return err;
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}
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static unsigned int
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nitrox_sym_dev_sess_get_size(__rte_unused struct rte_cryptodev *cdev)
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{
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return sizeof(struct nitrox_crypto_ctx);
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}
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static enum nitrox_chain
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get_crypto_chain_order(const struct rte_crypto_sym_xform *xform)
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{
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enum nitrox_chain res = NITROX_CHAIN_NOT_SUPPORTED;
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if (unlikely(xform == NULL))
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return res;
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switch (xform->type) {
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case RTE_CRYPTO_SYM_XFORM_AUTH:
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if (xform->next == NULL) {
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res = NITROX_CHAIN_NOT_SUPPORTED;
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} else if (xform->next->type == RTE_CRYPTO_SYM_XFORM_CIPHER) {
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if (xform->auth.op == RTE_CRYPTO_AUTH_OP_VERIFY &&
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xform->next->cipher.op ==
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RTE_CRYPTO_CIPHER_OP_DECRYPT) {
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res = NITROX_CHAIN_AUTH_CIPHER;
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} else {
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NITROX_LOG(ERR, "auth op %d, cipher op %d\n",
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xform->auth.op, xform->next->cipher.op);
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}
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}
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break;
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case RTE_CRYPTO_SYM_XFORM_CIPHER:
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if (xform->next == NULL) {
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res = NITROX_CHAIN_CIPHER_ONLY;
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} else if (xform->next->type == RTE_CRYPTO_SYM_XFORM_AUTH) {
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if (xform->cipher.op == RTE_CRYPTO_CIPHER_OP_ENCRYPT &&
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xform->next->auth.op ==
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RTE_CRYPTO_AUTH_OP_GENERATE) {
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res = NITROX_CHAIN_CIPHER_AUTH;
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} else {
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NITROX_LOG(ERR, "cipher op %d, auth op %d\n",
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xform->cipher.op, xform->next->auth.op);
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}
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}
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break;
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case RTE_CRYPTO_SYM_XFORM_AEAD:
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res = NITROX_CHAIN_COMBINED;
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break;
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default:
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break;
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}
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return res;
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}
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static enum flexi_cipher
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get_flexi_cipher_type(enum rte_crypto_cipher_algorithm algo, bool *is_aes)
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{
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enum flexi_cipher type;
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switch (algo) {
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case RTE_CRYPTO_CIPHER_AES_CBC:
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type = CIPHER_AES_CBC;
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*is_aes = true;
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break;
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case RTE_CRYPTO_CIPHER_3DES_CBC:
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type = CIPHER_3DES_CBC;
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*is_aes = false;
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break;
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default:
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type = CIPHER_INVALID;
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NITROX_LOG(ERR, "Algorithm not supported %d\n", algo);
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break;
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}
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return type;
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}
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static int
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flexi_aes_keylen(size_t keylen, bool is_aes)
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{
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int aes_keylen;
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if (!is_aes)
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return 0;
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switch (keylen) {
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case AES_KEYSIZE_128:
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aes_keylen = 1;
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break;
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case AES_KEYSIZE_192:
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aes_keylen = 2;
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break;
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case AES_KEYSIZE_256:
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aes_keylen = 3;
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break;
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default:
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NITROX_LOG(ERR, "Invalid keylen %zu\n", keylen);
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aes_keylen = -EINVAL;
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break;
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}
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return aes_keylen;
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}
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static bool
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crypto_key_is_valid(struct rte_crypto_cipher_xform *xform,
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struct flexi_crypto_context *fctx)
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{
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if (unlikely(xform->key.length > sizeof(fctx->crypto.key))) {
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NITROX_LOG(ERR, "Invalid crypto key length %d\n",
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xform->key.length);
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return false;
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}
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return true;
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}
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static int
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configure_cipher_ctx(struct rte_crypto_cipher_xform *xform,
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struct nitrox_crypto_ctx *ctx)
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{
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enum flexi_cipher type;
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bool cipher_is_aes = false;
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int aes_keylen;
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struct flexi_crypto_context *fctx = &ctx->fctx;
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type = get_flexi_cipher_type(xform->algo, &cipher_is_aes);
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if (unlikely(type == CIPHER_INVALID))
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return -ENOTSUP;
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aes_keylen = flexi_aes_keylen(xform->key.length, cipher_is_aes);
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if (unlikely(aes_keylen < 0))
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return -EINVAL;
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if (unlikely(!cipher_is_aes && !crypto_key_is_valid(xform, fctx)))
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return -EINVAL;
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if (unlikely(xform->iv.length > MAX_IV_LEN))
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return -EINVAL;
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fctx->flags = rte_be_to_cpu_64(fctx->flags);
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fctx->w0.cipher_type = type;
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fctx->w0.aes_keylen = aes_keylen;
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fctx->w0.iv_source = IV_FROM_DPTR;
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fctx->flags = rte_cpu_to_be_64(fctx->flags);
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memset(fctx->crypto.key, 0, sizeof(fctx->crypto.key));
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memcpy(fctx->crypto.key, xform->key.data, xform->key.length);
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ctx->opcode = FLEXI_CRYPTO_ENCRYPT_HMAC;
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ctx->req_op = (xform->op == RTE_CRYPTO_CIPHER_OP_ENCRYPT) ?
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NITROX_OP_ENCRYPT : NITROX_OP_DECRYPT;
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ctx->iv.offset = xform->iv.offset;
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ctx->iv.length = xform->iv.length;
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return 0;
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}
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static enum flexi_auth
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get_flexi_auth_type(enum rte_crypto_auth_algorithm algo)
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{
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enum flexi_auth type;
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switch (algo) {
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case RTE_CRYPTO_AUTH_SHA1_HMAC:
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type = AUTH_SHA1;
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break;
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case RTE_CRYPTO_AUTH_SHA224_HMAC:
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type = AUTH_SHA2_SHA224;
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break;
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case RTE_CRYPTO_AUTH_SHA256_HMAC:
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type = AUTH_SHA2_SHA256;
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break;
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default:
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NITROX_LOG(ERR, "Algorithm not supported %d\n", algo);
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type = AUTH_INVALID;
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break;
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}
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return type;
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}
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static bool
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auth_key_is_valid(const uint8_t *data, uint16_t length,
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struct flexi_crypto_context *fctx)
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{
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if (unlikely(!data && length)) {
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NITROX_LOG(ERR, "Invalid auth key\n");
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return false;
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}
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if (unlikely(length > sizeof(fctx->auth.opad))) {
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NITROX_LOG(ERR, "Invalid auth key length %d\n",
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length);
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return false;
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}
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return true;
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}
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static int
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configure_auth_ctx(struct rte_crypto_auth_xform *xform,
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struct nitrox_crypto_ctx *ctx)
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{
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enum flexi_auth type;
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struct flexi_crypto_context *fctx = &ctx->fctx;
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type = get_flexi_auth_type(xform->algo);
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if (unlikely(type == AUTH_INVALID))
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return -ENOTSUP;
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if (unlikely(!auth_key_is_valid(xform->key.data, xform->key.length,
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fctx)))
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return -EINVAL;
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ctx->digest_length = xform->digest_length;
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fctx->flags = rte_be_to_cpu_64(fctx->flags);
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fctx->w0.hash_type = type;
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fctx->w0.auth_input_type = 1;
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fctx->w0.mac_len = xform->digest_length;
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fctx->flags = rte_cpu_to_be_64(fctx->flags);
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memset(&fctx->auth, 0, sizeof(fctx->auth));
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memcpy(fctx->auth.opad, xform->key.data, xform->key.length);
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return 0;
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}
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static int
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configure_aead_ctx(struct rte_crypto_aead_xform *xform,
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struct nitrox_crypto_ctx *ctx)
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{
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int aes_keylen;
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struct flexi_crypto_context *fctx = &ctx->fctx;
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if (unlikely(xform->aad_length > FLEXI_CRYPTO_MAX_AAD_LEN)) {
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NITROX_LOG(ERR, "AAD length %d not supported\n",
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xform->aad_length);
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return -ENOTSUP;
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}
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if (unlikely(xform->algo != RTE_CRYPTO_AEAD_AES_GCM))
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return -ENOTSUP;
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aes_keylen = flexi_aes_keylen(xform->key.length, true);
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|
if (unlikely(aes_keylen < 0))
|
|
return -EINVAL;
|
|
|
|
if (unlikely(!auth_key_is_valid(xform->key.data, xform->key.length,
|
|
fctx)))
|
|
return -EINVAL;
|
|
|
|
if (unlikely(xform->iv.length > MAX_IV_LEN))
|
|
return -EINVAL;
|
|
|
|
fctx->flags = rte_be_to_cpu_64(fctx->flags);
|
|
fctx->w0.cipher_type = CIPHER_AES_GCM;
|
|
fctx->w0.aes_keylen = aes_keylen;
|
|
fctx->w0.iv_source = IV_FROM_DPTR;
|
|
fctx->w0.hash_type = AUTH_NULL;
|
|
fctx->w0.auth_input_type = 1;
|
|
fctx->w0.mac_len = xform->digest_length;
|
|
fctx->flags = rte_cpu_to_be_64(fctx->flags);
|
|
memset(fctx->crypto.key, 0, sizeof(fctx->crypto.key));
|
|
memcpy(fctx->crypto.key, xform->key.data, xform->key.length);
|
|
memset(&fctx->auth, 0, sizeof(fctx->auth));
|
|
memcpy(fctx->auth.opad, xform->key.data, xform->key.length);
|
|
|
|
ctx->opcode = FLEXI_CRYPTO_ENCRYPT_HMAC;
|
|
ctx->req_op = (xform->op == RTE_CRYPTO_AEAD_OP_ENCRYPT) ?
|
|
NITROX_OP_ENCRYPT : NITROX_OP_DECRYPT;
|
|
ctx->iv.offset = xform->iv.offset;
|
|
ctx->iv.length = xform->iv.length;
|
|
ctx->digest_length = xform->digest_length;
|
|
ctx->aad_length = xform->aad_length;
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
nitrox_sym_dev_sess_configure(struct rte_cryptodev *cdev,
|
|
struct rte_crypto_sym_xform *xform,
|
|
struct rte_cryptodev_sym_session *sess,
|
|
struct rte_mempool *mempool)
|
|
{
|
|
void *mp_obj;
|
|
struct nitrox_crypto_ctx *ctx;
|
|
struct rte_crypto_cipher_xform *cipher_xform = NULL;
|
|
struct rte_crypto_auth_xform *auth_xform = NULL;
|
|
struct rte_crypto_aead_xform *aead_xform = NULL;
|
|
int ret = -EINVAL;
|
|
|
|
if (rte_mempool_get(mempool, &mp_obj)) {
|
|
NITROX_LOG(ERR, "Couldn't allocate context\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
ctx = mp_obj;
|
|
ctx->nitrox_chain = get_crypto_chain_order(xform);
|
|
switch (ctx->nitrox_chain) {
|
|
case NITROX_CHAIN_CIPHER_ONLY:
|
|
cipher_xform = &xform->cipher;
|
|
break;
|
|
case NITROX_CHAIN_CIPHER_AUTH:
|
|
cipher_xform = &xform->cipher;
|
|
auth_xform = &xform->next->auth;
|
|
break;
|
|
case NITROX_CHAIN_AUTH_CIPHER:
|
|
auth_xform = &xform->auth;
|
|
cipher_xform = &xform->next->cipher;
|
|
break;
|
|
case NITROX_CHAIN_COMBINED:
|
|
aead_xform = &xform->aead;
|
|
break;
|
|
default:
|
|
NITROX_LOG(ERR, "Crypto chain not supported\n");
|
|
ret = -ENOTSUP;
|
|
goto err;
|
|
}
|
|
|
|
if (cipher_xform && unlikely(configure_cipher_ctx(cipher_xform, ctx))) {
|
|
NITROX_LOG(ERR, "Failed to configure cipher ctx\n");
|
|
goto err;
|
|
}
|
|
|
|
if (auth_xform && unlikely(configure_auth_ctx(auth_xform, ctx))) {
|
|
NITROX_LOG(ERR, "Failed to configure auth ctx\n");
|
|
goto err;
|
|
}
|
|
|
|
if (aead_xform && unlikely(configure_aead_ctx(aead_xform, ctx))) {
|
|
NITROX_LOG(ERR, "Failed to configure aead ctx\n");
|
|
goto err;
|
|
}
|
|
|
|
ctx->iova = rte_mempool_virt2iova(ctx);
|
|
set_sym_session_private_data(sess, cdev->driver_id, ctx);
|
|
return 0;
|
|
err:
|
|
rte_mempool_put(mempool, mp_obj);
|
|
return ret;
|
|
}
|
|
|
|
static void
|
|
nitrox_sym_dev_sess_clear(struct rte_cryptodev *cdev,
|
|
struct rte_cryptodev_sym_session *sess)
|
|
{
|
|
struct nitrox_crypto_ctx *ctx = get_sym_session_private_data(sess,
|
|
cdev->driver_id);
|
|
struct rte_mempool *sess_mp;
|
|
|
|
if (!ctx)
|
|
return;
|
|
|
|
memset(ctx, 0, sizeof(*ctx));
|
|
sess_mp = rte_mempool_from_obj(ctx);
|
|
set_sym_session_private_data(sess, cdev->driver_id, NULL);
|
|
rte_mempool_put(sess_mp, ctx);
|
|
}
|
|
|
|
static struct nitrox_crypto_ctx *
|
|
get_crypto_ctx(struct rte_crypto_op *op)
|
|
{
|
|
if (op->sess_type == RTE_CRYPTO_OP_WITH_SESSION) {
|
|
if (likely(op->sym->session))
|
|
return get_sym_session_private_data(op->sym->session,
|
|
nitrox_sym_drv_id);
|
|
}
|
|
|
|
return NULL;
|
|
}
|
|
|
|
static int
|
|
nitrox_enq_single_op(struct nitrox_qp *qp, struct rte_crypto_op *op)
|
|
{
|
|
struct nitrox_crypto_ctx *ctx;
|
|
struct nitrox_softreq *sr;
|
|
int err;
|
|
|
|
op->status = RTE_CRYPTO_OP_STATUS_NOT_PROCESSED;
|
|
ctx = get_crypto_ctx(op);
|
|
if (unlikely(!ctx)) {
|
|
op->status = RTE_CRYPTO_OP_STATUS_INVALID_SESSION;
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (unlikely(rte_mempool_get(qp->sr_mp, (void **)&sr)))
|
|
return -ENOMEM;
|
|
|
|
err = nitrox_process_se_req(qp->qno, op, ctx, sr);
|
|
if (unlikely(err)) {
|
|
rte_mempool_put(qp->sr_mp, sr);
|
|
op->status = RTE_CRYPTO_OP_STATUS_ERROR;
|
|
return err;
|
|
}
|
|
|
|
nitrox_qp_enqueue(qp, nitrox_sym_instr_addr(sr), sr);
|
|
return 0;
|
|
}
|
|
|
|
static uint16_t
|
|
nitrox_sym_dev_enq_burst(void *queue_pair, struct rte_crypto_op **ops,
|
|
uint16_t nb_ops)
|
|
{
|
|
struct nitrox_qp *qp = queue_pair;
|
|
uint16_t free_slots = 0;
|
|
uint16_t cnt = 0;
|
|
bool err = false;
|
|
|
|
free_slots = nitrox_qp_free_count(qp);
|
|
if (nb_ops > free_slots)
|
|
nb_ops = free_slots;
|
|
|
|
for (cnt = 0; cnt < nb_ops; cnt++) {
|
|
if (unlikely(nitrox_enq_single_op(qp, ops[cnt]))) {
|
|
err = true;
|
|
break;
|
|
}
|
|
}
|
|
|
|
nitrox_ring_dbell(qp, cnt);
|
|
qp->stats.enqueued_count += cnt;
|
|
if (unlikely(err))
|
|
qp->stats.enqueue_err_count++;
|
|
|
|
return cnt;
|
|
}
|
|
|
|
static int
|
|
nitrox_deq_single_op(struct nitrox_qp *qp, struct rte_crypto_op **op_ptr)
|
|
{
|
|
struct nitrox_softreq *sr;
|
|
int ret;
|
|
struct rte_crypto_op *op;
|
|
|
|
sr = nitrox_qp_get_softreq(qp);
|
|
ret = nitrox_check_se_req(sr, op_ptr);
|
|
if (ret < 0)
|
|
return -EAGAIN;
|
|
|
|
op = *op_ptr;
|
|
nitrox_qp_dequeue(qp);
|
|
rte_mempool_put(qp->sr_mp, sr);
|
|
if (!ret) {
|
|
op->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
|
|
qp->stats.dequeued_count++;
|
|
|
|
return 0;
|
|
}
|
|
|
|
if (ret == MC_MAC_MISMATCH_ERR_CODE)
|
|
op->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;
|
|
else
|
|
op->status = RTE_CRYPTO_OP_STATUS_ERROR;
|
|
|
|
qp->stats.dequeue_err_count++;
|
|
return 0;
|
|
}
|
|
|
|
static uint16_t
|
|
nitrox_sym_dev_deq_burst(void *queue_pair, struct rte_crypto_op **ops,
|
|
uint16_t nb_ops)
|
|
{
|
|
struct nitrox_qp *qp = queue_pair;
|
|
uint16_t filled_slots = nitrox_qp_used_count(qp);
|
|
int cnt = 0;
|
|
|
|
if (nb_ops > filled_slots)
|
|
nb_ops = filled_slots;
|
|
|
|
for (cnt = 0; cnt < nb_ops; cnt++)
|
|
if (nitrox_deq_single_op(qp, &ops[cnt]))
|
|
break;
|
|
|
|
return cnt;
|
|
}
|
|
|
|
static struct rte_cryptodev_ops nitrox_cryptodev_ops = {
|
|
.dev_configure = nitrox_sym_dev_config,
|
|
.dev_start = nitrox_sym_dev_start,
|
|
.dev_stop = nitrox_sym_dev_stop,
|
|
.dev_close = nitrox_sym_dev_close,
|
|
.dev_infos_get = nitrox_sym_dev_info_get,
|
|
.stats_get = nitrox_sym_dev_stats_get,
|
|
.stats_reset = nitrox_sym_dev_stats_reset,
|
|
.queue_pair_setup = nitrox_sym_dev_qp_setup,
|
|
.queue_pair_release = nitrox_sym_dev_qp_release,
|
|
.sym_session_get_size = nitrox_sym_dev_sess_get_size,
|
|
.sym_session_configure = nitrox_sym_dev_sess_configure,
|
|
.sym_session_clear = nitrox_sym_dev_sess_clear
|
|
};
|
|
|
|
int
|
|
nitrox_sym_pmd_create(struct nitrox_device *ndev)
|
|
{
|
|
char name[RTE_CRYPTODEV_NAME_MAX_LEN];
|
|
struct rte_cryptodev_pmd_init_params init_params = {
|
|
.name = "",
|
|
.socket_id = ndev->pdev->device.numa_node,
|
|
.private_data_size = sizeof(struct nitrox_sym_device)
|
|
};
|
|
struct rte_cryptodev *cdev;
|
|
|
|
rte_pci_device_name(&ndev->pdev->addr, name, sizeof(name));
|
|
snprintf(name + strlen(name), RTE_CRYPTODEV_NAME_MAX_LEN - strlen(name),
|
|
"_n5sym");
|
|
ndev->rte_sym_dev.driver = &nitrox_rte_sym_drv;
|
|
ndev->rte_sym_dev.numa_node = ndev->pdev->device.numa_node;
|
|
ndev->rte_sym_dev.devargs = NULL;
|
|
cdev = rte_cryptodev_pmd_create(name, &ndev->rte_sym_dev,
|
|
&init_params);
|
|
if (!cdev) {
|
|
NITROX_LOG(ERR, "Cryptodev '%s' creation failed\n", name);
|
|
return -ENODEV;
|
|
}
|
|
|
|
ndev->rte_sym_dev.name = cdev->data->name;
|
|
cdev->driver_id = nitrox_sym_drv_id;
|
|
cdev->dev_ops = &nitrox_cryptodev_ops;
|
|
cdev->enqueue_burst = nitrox_sym_dev_enq_burst;
|
|
cdev->dequeue_burst = nitrox_sym_dev_deq_burst;
|
|
cdev->feature_flags = RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO |
|
|
RTE_CRYPTODEV_FF_HW_ACCELERATED |
|
|
RTE_CRYPTODEV_FF_SYM_OPERATION_CHAINING |
|
|
RTE_CRYPTODEV_FF_IN_PLACE_SGL |
|
|
RTE_CRYPTODEV_FF_OOP_SGL_IN_SGL_OUT |
|
|
RTE_CRYPTODEV_FF_OOP_SGL_IN_LB_OUT |
|
|
RTE_CRYPTODEV_FF_OOP_LB_IN_SGL_OUT |
|
|
RTE_CRYPTODEV_FF_OOP_LB_IN_LB_OUT;
|
|
|
|
ndev->sym_dev = cdev->data->dev_private;
|
|
ndev->sym_dev->cdev = cdev;
|
|
ndev->sym_dev->ndev = ndev;
|
|
NITROX_LOG(DEBUG, "Created cryptodev '%s', dev_id %d, drv_id %d\n",
|
|
cdev->data->name, cdev->data->dev_id, nitrox_sym_drv_id);
|
|
return 0;
|
|
}
|
|
|
|
int
|
|
nitrox_sym_pmd_destroy(struct nitrox_device *ndev)
|
|
{
|
|
return rte_cryptodev_pmd_destroy(ndev->sym_dev->cdev);
|
|
}
|
|
|
|
static struct cryptodev_driver nitrox_crypto_drv;
|
|
RTE_PMD_REGISTER_CRYPTO_DRIVER(nitrox_crypto_drv,
|
|
nitrox_rte_sym_drv,
|
|
nitrox_sym_drv_id);
|