05fa3d4a65
Defined FPGA-BUS for Acceleration Drivers of AFUs 1. FPGA PCI Scan (1st Scan) follows DPDK UIO/VFIO PCI Scan Process, probe Intel FPGA Rawdev Driver, it will be covered in following patches. 2. AFU Scan(2nd Scan) bind DPDK driver to FPGA Partial-Bitstream. This scan is trigged by hotplug of IFPGA Rawdev probe, in this scan the AFUs will be created and their drivers are also probed. This patch will introduce rte_afu_device which describe the AFU device listed in the FPGA-BUS. Signed-off-by: Rosen Xu <rosen.xu@intel.com> Signed-off-by: Tianfei Zhang <tianfei.zhang@intel.com> Reviewed-by: Qi Zhang <qi.z.zhang@intel.com>
8 lines
221 B
Meson
8 lines
221 B
Meson
# SPDX-License-Identifier: BSD-3-Clause
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# Copyright(c) 2017 Intel Corporation
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drivers = ['dpaa', 'fslmc', 'ifpga', 'pci', 'vdev']
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std_deps = ['eal']
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config_flag_fmt = 'RTE_LIBRTE_@0@_BUS'
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driver_name_fmt = 'rte_bus_@0@'
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