dac12650eb
Add support to retrieve dev infos get for CN9K and CN10K. Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
72 lines
2.1 KiB
C
72 lines
2.1 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(C) 2021 Marvell.
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*/
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#include <cnxk_ethdev.h>
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int
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cnxk_nix_info_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *devinfo)
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{
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struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
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struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
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int max_rx_pktlen;
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max_rx_pktlen = (roc_nix_max_pkt_len(&dev->nix) + RTE_ETHER_CRC_LEN -
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CNXK_NIX_MAX_VTAG_ACT_SIZE);
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devinfo->min_rx_bufsize = NIX_MIN_HW_FRS + RTE_ETHER_CRC_LEN;
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devinfo->max_rx_pktlen = max_rx_pktlen;
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devinfo->max_rx_queues = RTE_MAX_QUEUES_PER_PORT;
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devinfo->max_tx_queues = RTE_MAX_QUEUES_PER_PORT;
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devinfo->max_mac_addrs = dev->max_mac_entries;
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devinfo->max_vfs = pci_dev->max_vfs;
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devinfo->max_mtu = devinfo->max_rx_pktlen - CNXK_NIX_L2_OVERHEAD;
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devinfo->min_mtu = devinfo->min_rx_bufsize - CNXK_NIX_L2_OVERHEAD;
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devinfo->rx_offload_capa = dev->rx_offload_capa;
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devinfo->tx_offload_capa = dev->tx_offload_capa;
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devinfo->rx_queue_offload_capa = 0;
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devinfo->tx_queue_offload_capa = 0;
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devinfo->reta_size = dev->nix.reta_sz;
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devinfo->hash_key_size = ROC_NIX_RSS_KEY_LEN;
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devinfo->flow_type_rss_offloads = CNXK_NIX_RSS_OFFLOAD;
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devinfo->default_rxconf = (struct rte_eth_rxconf){
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.rx_drop_en = 0,
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.offloads = 0,
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};
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devinfo->default_txconf = (struct rte_eth_txconf){
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.offloads = 0,
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};
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devinfo->default_rxportconf = (struct rte_eth_dev_portconf){
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.ring_size = CNXK_NIX_RX_DEFAULT_RING_SZ,
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};
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devinfo->rx_desc_lim = (struct rte_eth_desc_lim){
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.nb_max = UINT16_MAX,
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.nb_min = CNXK_NIX_RX_MIN_DESC,
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.nb_align = CNXK_NIX_RX_MIN_DESC_ALIGN,
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.nb_seg_max = CNXK_NIX_RX_NB_SEG_MAX,
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.nb_mtu_seg_max = CNXK_NIX_RX_NB_SEG_MAX,
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};
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devinfo->rx_desc_lim.nb_max =
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RTE_ALIGN_MUL_FLOOR(devinfo->rx_desc_lim.nb_max,
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CNXK_NIX_RX_MIN_DESC_ALIGN);
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devinfo->tx_desc_lim = (struct rte_eth_desc_lim){
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.nb_max = UINT16_MAX,
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.nb_min = 1,
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.nb_align = 1,
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.nb_seg_max = CNXK_NIX_TX_NB_SEG_MAX,
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.nb_mtu_seg_max = CNXK_NIX_TX_NB_SEG_MAX,
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};
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devinfo->speed_capa = dev->speed_capa;
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devinfo->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
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RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
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return 0;
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}
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