3983583414
Add bnxt vector PMD support using NEON SIMD instructions. Also update the 20.08 release notes with this information. Signed-off-by: Lance Richardson <lance.richardson@broadcom.com> Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com> Reviewed-by: Ruifeng Wang <ruifeng.wang@arm.com>
470 lines
12 KiB
C
470 lines
12 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause */
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/* Copyright(c) 2019-2020 Broadcom All rights reserved. */
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#include <inttypes.h>
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#include <stdbool.h>
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#include <rte_bitmap.h>
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#include <rte_byteorder.h>
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#include <rte_malloc.h>
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#include <rte_memory.h>
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#include <rte_vect.h>
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#include "bnxt.h"
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#include "bnxt_cpr.h"
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#include "bnxt_ring.h"
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#include "bnxt_rxr.h"
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#include "bnxt_rxq.h"
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#include "hsi_struct_def_dpdk.h"
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#include "bnxt_rxtx_vec_common.h"
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#include "bnxt_txq.h"
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#include "bnxt_txr.h"
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/*
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* RX Ring handling
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*/
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static inline void
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bnxt_rxq_rearm(struct bnxt_rx_queue *rxq, struct bnxt_rx_ring_info *rxr)
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{
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struct rx_prod_pkt_bd *rxbds = &rxr->rx_desc_ring[rxq->rxrearm_start];
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struct bnxt_sw_rx_bd *rx_bufs = &rxr->rx_buf_ring[rxq->rxrearm_start];
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struct rte_mbuf *mb0, *mb1;
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int i;
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const uint64x2_t hdr_room = {0, RTE_PKTMBUF_HEADROOM};
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const uint64x2_t addrmask = {0, UINT64_MAX};
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/* Pull RTE_BNXT_RXQ_REARM_THRESH more mbufs into the software ring */
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if (rte_mempool_get_bulk(rxq->mb_pool,
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(void *)rx_bufs,
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RTE_BNXT_RXQ_REARM_THRESH) < 0) {
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rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
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RTE_BNXT_RXQ_REARM_THRESH;
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return;
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}
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/* Initialize the mbufs in vector, process 2 mbufs in one loop */
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for (i = 0; i < RTE_BNXT_RXQ_REARM_THRESH; i += 2, rx_bufs += 2) {
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uint64x2_t buf_addr0, buf_addr1;
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uint64x2_t rxbd0, rxbd1;
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mb0 = rx_bufs[0].mbuf;
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mb1 = rx_bufs[1].mbuf;
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/* Load address fields from both mbufs */
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buf_addr0 = vld1q_u64((uint64_t *)&mb0->buf_addr);
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buf_addr1 = vld1q_u64((uint64_t *)&mb1->buf_addr);
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/* Load both rx descriptors (preserving some existing fields) */
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rxbd0 = vld1q_u64((uint64_t *)(rxbds + 0));
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rxbd1 = vld1q_u64((uint64_t *)(rxbds + 1));
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/* Add default offset to buffer address. */
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buf_addr0 = vaddq_u64(buf_addr0, hdr_room);
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buf_addr1 = vaddq_u64(buf_addr1, hdr_room);
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/* Clear all fields except address. */
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buf_addr0 = vandq_u64(buf_addr0, addrmask);
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buf_addr1 = vandq_u64(buf_addr1, addrmask);
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/* Clear address field in descriptor. */
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rxbd0 = vbicq_u64(rxbd0, addrmask);
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rxbd1 = vbicq_u64(rxbd1, addrmask);
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/* Set address field in descriptor. */
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rxbd0 = vaddq_u64(rxbd0, buf_addr0);
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rxbd1 = vaddq_u64(rxbd1, buf_addr1);
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/* Store descriptors to memory. */
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vst1q_u64((uint64_t *)(rxbds++), rxbd0);
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vst1q_u64((uint64_t *)(rxbds++), rxbd1);
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}
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rxq->rxrearm_start += RTE_BNXT_RXQ_REARM_THRESH;
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bnxt_db_write(&rxr->rx_db, rxq->rxrearm_start - 1);
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if (rxq->rxrearm_start >= rxq->nb_rx_desc)
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rxq->rxrearm_start = 0;
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rxq->rxrearm_nb -= RTE_BNXT_RXQ_REARM_THRESH;
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}
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static uint32_t
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bnxt_parse_pkt_type(struct rx_pkt_cmpl *rxcmp, struct rx_pkt_cmpl_hi *rxcmp1)
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{
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uint32_t l3, pkt_type = 0;
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uint32_t t_ipcs = 0, ip6 = 0, vlan = 0;
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uint32_t flags_type;
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vlan = !!(rxcmp1->flags2 &
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rte_cpu_to_le_32(RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN));
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pkt_type |= vlan ? RTE_PTYPE_L2_ETHER_VLAN : RTE_PTYPE_L2_ETHER;
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t_ipcs = !!(rxcmp1->flags2 &
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rte_cpu_to_le_32(RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC));
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ip6 = !!(rxcmp1->flags2 &
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rte_cpu_to_le_32(RX_PKT_CMPL_FLAGS2_IP_TYPE));
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flags_type = rxcmp->flags_type &
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rte_cpu_to_le_32(RX_PKT_CMPL_FLAGS_ITYPE_MASK);
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if (!t_ipcs && !ip6)
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l3 = RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
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else if (!t_ipcs && ip6)
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l3 = RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
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else if (t_ipcs && !ip6)
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l3 = RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
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else
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l3 = RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
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switch (flags_type) {
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case RTE_LE32(RX_PKT_CMPL_FLAGS_ITYPE_ICMP):
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if (!t_ipcs)
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pkt_type |= l3 | RTE_PTYPE_L4_ICMP;
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else
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pkt_type |= l3 | RTE_PTYPE_INNER_L4_ICMP;
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break;
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case RTE_LE32(RX_PKT_CMPL_FLAGS_ITYPE_TCP):
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if (!t_ipcs)
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pkt_type |= l3 | RTE_PTYPE_L4_TCP;
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else
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pkt_type |= l3 | RTE_PTYPE_INNER_L4_TCP;
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break;
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case RTE_LE32(RX_PKT_CMPL_FLAGS_ITYPE_UDP):
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if (!t_ipcs)
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pkt_type |= l3 | RTE_PTYPE_L4_UDP;
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else
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pkt_type |= l3 | RTE_PTYPE_INNER_L4_UDP;
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break;
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case RTE_LE32(RX_PKT_CMPL_FLAGS_ITYPE_IP):
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pkt_type |= l3;
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break;
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}
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return pkt_type;
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}
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static void
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bnxt_parse_csum(struct rte_mbuf *mbuf, struct rx_pkt_cmpl_hi *rxcmp1)
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{
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uint32_t flags;
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flags = flags2_0xf(rxcmp1);
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/* IP Checksum */
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if (likely(IS_IP_NONTUNNEL_PKT(flags))) {
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if (unlikely(RX_CMP_IP_CS_ERROR(rxcmp1)))
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mbuf->ol_flags |= PKT_RX_IP_CKSUM_BAD;
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else
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mbuf->ol_flags |= PKT_RX_IP_CKSUM_GOOD;
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} else if (IS_IP_TUNNEL_PKT(flags)) {
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if (unlikely(RX_CMP_IP_OUTER_CS_ERROR(rxcmp1) ||
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RX_CMP_IP_CS_ERROR(rxcmp1)))
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mbuf->ol_flags |= PKT_RX_IP_CKSUM_BAD;
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else
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mbuf->ol_flags |= PKT_RX_IP_CKSUM_GOOD;
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} else if (unlikely(RX_CMP_IP_CS_UNKNOWN(rxcmp1))) {
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mbuf->ol_flags |= PKT_RX_IP_CKSUM_UNKNOWN;
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}
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/* L4 Checksum */
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if (likely(IS_L4_NONTUNNEL_PKT(flags))) {
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if (unlikely(RX_CMP_L4_INNER_CS_ERR2(rxcmp1)))
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mbuf->ol_flags |= PKT_RX_L4_CKSUM_BAD;
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else
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mbuf->ol_flags |= PKT_RX_L4_CKSUM_GOOD;
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} else if (IS_L4_TUNNEL_PKT(flags)) {
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if (unlikely(RX_CMP_L4_INNER_CS_ERR2(rxcmp1)))
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mbuf->ol_flags |= PKT_RX_L4_CKSUM_BAD;
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else
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mbuf->ol_flags |= PKT_RX_L4_CKSUM_GOOD;
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if (unlikely(RX_CMP_L4_OUTER_CS_ERR2(rxcmp1))) {
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mbuf->ol_flags |= PKT_RX_OUTER_L4_CKSUM_BAD;
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} else if (unlikely(IS_L4_TUNNEL_PKT_ONLY_INNER_L4_CS
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(flags))) {
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mbuf->ol_flags |= PKT_RX_OUTER_L4_CKSUM_UNKNOWN;
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} else {
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mbuf->ol_flags |= PKT_RX_OUTER_L4_CKSUM_GOOD;
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}
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} else if (unlikely(RX_CMP_L4_CS_UNKNOWN(rxcmp1))) {
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mbuf->ol_flags |= PKT_RX_L4_CKSUM_UNKNOWN;
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}
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}
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uint16_t
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bnxt_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
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uint16_t nb_pkts)
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{
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struct bnxt_rx_queue *rxq = rx_queue;
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struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
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struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
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uint32_t raw_cons = cpr->cp_raw_cons;
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uint32_t cons;
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int nb_rx_pkts = 0;
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struct rx_pkt_cmpl *rxcmp;
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bool evt = false;
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const uint64x2_t mbuf_init = {rxq->mbuf_initializer, 0};
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const uint8x16_t shuf_msk = {
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0xFF, 0xFF, 0xFF, 0xFF, /* pkt_type (zeroes) */
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2, 3, 0xFF, 0xFF, /* pkt_len */
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2, 3, /* data_len */
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0xFF, 0xFF, /* vlan_tci (zeroes) */
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12, 13, 14, 15 /* rss hash */
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};
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/* If Rx Q was stopped return */
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if (unlikely(!rxq->rx_started))
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return 0;
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if (rxq->rxrearm_nb >= RTE_BNXT_RXQ_REARM_THRESH)
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bnxt_rxq_rearm(rxq, rxr);
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/* Return no more than RTE_BNXT_MAX_RX_BURST per call. */
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nb_pkts = RTE_MIN(nb_pkts, RTE_BNXT_MAX_RX_BURST);
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/* Make nb_pkts an integer multiple of RTE_BNXT_DESCS_PER_LOOP */
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nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, RTE_BNXT_DESCS_PER_LOOP);
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if (!nb_pkts)
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return 0;
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/* Handle RX burst request */
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while (1) {
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cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
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rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
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if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct))
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break;
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if (likely(CMP_TYPE(rxcmp) == RX_PKT_CMPL_TYPE_RX_L2)) {
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struct rx_pkt_cmpl_hi *rxcmp1;
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uint32_t tmp_raw_cons;
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uint16_t cp_cons;
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struct rte_mbuf *mbuf;
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uint64x2_t mm_rxcmp;
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uint8x16_t pkt_mb;
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tmp_raw_cons = NEXT_RAW_CMP(raw_cons);
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cp_cons = RING_CMP(cpr->cp_ring_struct, tmp_raw_cons);
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rxcmp1 = (struct rx_pkt_cmpl_hi *)
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&cpr->cp_desc_ring[cp_cons];
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if (!CMP_VALID(rxcmp1, tmp_raw_cons,
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cpr->cp_ring_struct))
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break;
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raw_cons = tmp_raw_cons;
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cons = rxcmp->opaque;
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mbuf = rxr->rx_buf_ring[cons].mbuf;
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rte_prefetch0(mbuf);
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rxr->rx_buf_ring[cons].mbuf = NULL;
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/* Set constant fields from mbuf initializer. */
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vst1q_u64((uint64_t *)&mbuf->rearm_data, mbuf_init);
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/* Set mbuf pkt_len, data_len, and rss_hash fields. */
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mm_rxcmp = vld1q_u64((uint64_t *)rxcmp);
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pkt_mb = vqtbl1q_u8(vreinterpretq_u8_u64(mm_rxcmp),
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shuf_msk);
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vst1q_u64((uint64_t *)&mbuf->rx_descriptor_fields1,
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vreinterpretq_u64_u8(pkt_mb));
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rte_compiler_barrier();
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if (rxcmp->flags_type & RX_PKT_CMPL_FLAGS_RSS_VALID)
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mbuf->ol_flags |= PKT_RX_RSS_HASH;
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if (rxcmp1->flags2 &
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RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN) {
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mbuf->vlan_tci = rxcmp1->metadata &
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(RX_PKT_CMPL_METADATA_VID_MASK |
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RX_PKT_CMPL_METADATA_DE |
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RX_PKT_CMPL_METADATA_PRI_MASK);
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mbuf->ol_flags |=
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PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
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}
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bnxt_parse_csum(mbuf, rxcmp1);
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mbuf->packet_type = bnxt_parse_pkt_type(rxcmp, rxcmp1);
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rx_pkts[nb_rx_pkts++] = mbuf;
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} else if (!BNXT_NUM_ASYNC_CPR(rxq->bp)) {
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evt =
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bnxt_event_hwrm_resp_handler(rxq->bp,
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(struct cmpl_base *)rxcmp);
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}
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raw_cons = NEXT_RAW_CMP(raw_cons);
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if (nb_rx_pkts == nb_pkts || evt)
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break;
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}
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rxr->rx_prod = RING_ADV(rxr->rx_ring_struct, rxr->rx_prod, nb_rx_pkts);
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rxq->rxrearm_nb += nb_rx_pkts;
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cpr->cp_raw_cons = raw_cons;
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cpr->valid = !!(cpr->cp_raw_cons & cpr->cp_ring_struct->ring_size);
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if (nb_rx_pkts || evt)
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bnxt_db_cq(cpr);
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return nb_rx_pkts;
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}
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static void
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bnxt_tx_cmp_vec(struct bnxt_tx_queue *txq, int nr_pkts)
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{
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struct bnxt_tx_ring_info *txr = txq->tx_ring;
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struct rte_mbuf **free = txq->free;
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uint16_t cons = txr->tx_cons;
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unsigned int blk = 0;
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while (nr_pkts--) {
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struct bnxt_sw_tx_bd *tx_buf;
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struct rte_mbuf *mbuf;
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tx_buf = &txr->tx_buf_ring[cons];
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cons = RING_NEXT(txr->tx_ring_struct, cons);
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mbuf = rte_pktmbuf_prefree_seg(tx_buf->mbuf);
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tx_buf->mbuf = NULL;
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if (blk && mbuf->pool != free[0]->pool) {
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rte_mempool_put_bulk(free[0]->pool, (void **)free, blk);
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blk = 0;
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}
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free[blk++] = mbuf;
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}
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if (blk)
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rte_mempool_put_bulk(free[0]->pool, (void **)free, blk);
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txr->tx_cons = cons;
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}
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static void
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bnxt_handle_tx_cp_vec(struct bnxt_tx_queue *txq)
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{
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struct bnxt_cp_ring_info *cpr = txq->cp_ring;
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uint32_t raw_cons = cpr->cp_raw_cons;
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uint32_t cons;
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uint32_t nb_tx_pkts = 0;
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struct tx_cmpl *txcmp;
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struct cmpl_base *cp_desc_ring = cpr->cp_desc_ring;
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struct bnxt_ring *cp_ring_struct = cpr->cp_ring_struct;
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uint32_t ring_mask = cp_ring_struct->ring_mask;
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do {
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cons = RING_CMPL(ring_mask, raw_cons);
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txcmp = (struct tx_cmpl *)&cp_desc_ring[cons];
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if (!CMP_VALID(txcmp, raw_cons, cp_ring_struct))
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break;
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if (likely(CMP_TYPE(txcmp) == TX_CMPL_TYPE_TX_L2))
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nb_tx_pkts += txcmp->opaque;
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else
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RTE_LOG_DP(ERR, PMD,
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"Unhandled CMP type %02x\n",
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CMP_TYPE(txcmp));
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raw_cons = NEXT_RAW_CMP(raw_cons);
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} while (nb_tx_pkts < ring_mask);
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cpr->valid = !!(raw_cons & cp_ring_struct->ring_size);
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if (nb_tx_pkts) {
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bnxt_tx_cmp_vec(txq, nb_tx_pkts);
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cpr->cp_raw_cons = raw_cons;
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bnxt_db_cq(cpr);
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}
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}
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static uint16_t
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bnxt_xmit_fixed_burst_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
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uint16_t nb_pkts)
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{
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struct bnxt_tx_queue *txq = tx_queue;
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struct bnxt_tx_ring_info *txr = txq->tx_ring;
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uint16_t prod = txr->tx_prod;
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struct rte_mbuf *tx_mbuf;
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struct tx_bd_long *txbd = NULL;
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struct bnxt_sw_tx_bd *tx_buf;
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uint16_t to_send;
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nb_pkts = RTE_MIN(nb_pkts, bnxt_tx_avail(txq));
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if (unlikely(nb_pkts == 0))
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return 0;
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/* Handle TX burst request */
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to_send = nb_pkts;
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while (to_send) {
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tx_mbuf = *tx_pkts++;
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rte_prefetch0(tx_mbuf);
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tx_buf = &txr->tx_buf_ring[prod];
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tx_buf->mbuf = tx_mbuf;
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tx_buf->nr_bds = 1;
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txbd = &txr->tx_desc_ring[prod];
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txbd->address = tx_mbuf->buf_iova + tx_mbuf->data_off;
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txbd->len = tx_mbuf->data_len;
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txbd->flags_type = bnxt_xmit_flags_len(tx_mbuf->data_len,
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TX_BD_FLAGS_NOCMPL);
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prod = RING_NEXT(txr->tx_ring_struct, prod);
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to_send--;
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}
|
|
|
|
/* Request a completion for last packet in burst */
|
|
if (txbd) {
|
|
txbd->opaque = nb_pkts;
|
|
txbd->flags_type &= ~TX_BD_LONG_FLAGS_NO_CMPL;
|
|
}
|
|
|
|
rte_compiler_barrier();
|
|
bnxt_db_write(&txr->tx_db, prod);
|
|
|
|
txr->tx_prod = prod;
|
|
|
|
return nb_pkts;
|
|
}
|
|
|
|
uint16_t
|
|
bnxt_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
|
|
uint16_t nb_pkts)
|
|
{
|
|
int nb_sent = 0;
|
|
struct bnxt_tx_queue *txq = tx_queue;
|
|
|
|
/* Tx queue was stopped; wait for it to be restarted */
|
|
if (unlikely(!txq->tx_started)) {
|
|
PMD_DRV_LOG(DEBUG, "Tx q stopped;return\n");
|
|
return 0;
|
|
}
|
|
|
|
/* Handle TX completions */
|
|
if (bnxt_tx_bds_in_hw(txq) >= txq->tx_free_thresh)
|
|
bnxt_handle_tx_cp_vec(txq);
|
|
|
|
while (nb_pkts) {
|
|
uint16_t ret, num;
|
|
|
|
num = RTE_MIN(nb_pkts, RTE_BNXT_MAX_TX_BURST);
|
|
ret = bnxt_xmit_fixed_burst_vec(tx_queue,
|
|
&tx_pkts[nb_sent],
|
|
num);
|
|
nb_sent += ret;
|
|
nb_pkts -= ret;
|
|
if (ret < num)
|
|
break;
|
|
}
|
|
|
|
return nb_sent;
|
|
}
|
|
|
|
int __rte_cold
|
|
bnxt_rxq_vec_setup(struct bnxt_rx_queue *rxq)
|
|
{
|
|
return bnxt_rxq_vec_setup_common(rxq);
|
|
}
|